Method for Forming Chip-on-Wafer Assembly

• US 20130119552A1
• Filed: 11/16/2011
• Published: 05/16/2013
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Huang, Cheng-Lin, Lu, Szu Wei, Hung, Jui-Pin, Jeng, Shin-Puu, Yu, Chen-Hua
• Granted Patent: US 8,779,599 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Claims

1. A device comprising:

a bottom chip;

an active top die bonded to the bottom chip; and

a dummy die attached to the bottom chip, wherein the dummy die is electrically insulated from the bottom chip.

2. The device of claim 1, wherein the dummy die is selected from the group consisting essentially of a blank die free from integrated circuits therein, a silicon die free from low-k dielectric layers, metal lines, and vias therein, and combinations thereof.

3. The device of claim 1, wherein the dummy die is configured not to be coupled to power supply.

4. The device of claim 1, wherein the active top die is bonded to the bottom chip and electrically coupled to the bottom chip through electrical connectors, wherein the dummy die is adhered to the bottom chip through an adhesive, and wherein the dummy die is electrically insulated from the bottom chip by the adhesive.

5. The device of claim 1 further comprising a molding compound in a gap between the active top die and the dummy die.

6. The device of claim 1, wherein the bottom chip is a part of a wafer, and is not sawed from the wafer.

7. The device of claim 1, wherein the bottom chip further comprises a through-substrate via in a semiconductor substrate of the bottom chip.

8. A device comprising:

a bottom chip comprising;

a substrate;

a through-via extending from a first side to a second side of the substrate;

a first connector on the first side of the substrate; and

a second connector on the second side of the substrate, wherein the first connector is electrically coupled to the second connector through the through via;

an active top die on the first side of the substrate and bonded to the bottom chip through the first connector;

a dummy die on the first side of the substrate; and

a die-attach film attaching the dummy die to the bottom chip.

9. The device of claim 8, wherein the dummy die is configured not to be coupled to any power supply.

10. The device of claim 9, wherein the die-attach film comprises a dielectric material, and wherein no conductive feature penetrates through the die-attach film.

11. The device of claim 8 further comprising a molding compound in a gap between the active top die and the dummy die.

12. The device of claim 8, wherein the dummy die does not comprise active integrated circuits therein.

13. The device of claim 8, wherein the dummy die is a blank die not comprising any integrated circuit therein.

14. The device of claim 8, wherein the dummy die is a part a wafer, and is not sawed from the wafer.

15. A method comprising:

bonding a plurality of active top dies to a bottom wafer, wherein each of the plurality of active top dies is bonded to one of a plurality of identical chips in the bottom wafer through electrical connectors;

attaching a plurality of dummy dies to the plurality of identical chips, wherein each of the plurality of dummy dies is attached to one of the plurality of identical chips through one of a plurality of die-attach films, and wherein the plurality of dummy dies is electrically insulated from the plurality of identical chips by the plurality of die-attach films; and

filling a molding compound into gaps between the plurality of active top dies and the plurality of dummy dies.

16. The method of claim 15 further comprising, before the step of applying the molding compound, attaching a dummy die to an incomplete bottom chip in the bottom wafer, wherein the molding compound is in physical contact with the dummy die.

17. The method of claim 15 further comprising:

after the step of filling the molding compound, attaching a carrier to the bottom wafer using an adhesive;

performing a backside grinding to a substrate in the bottom wafer to expose a through-silicon via in the bottom wafer; and

forming a backside interconnect structure on a backside of the bottom wafer; and

sawing the bottom wafer to form a plurality of packages, wherein each of the plurality of packages comprises one of the plurality of active top dies and one of the plurality of dummy dies.

18. The method of claim 15, wherein no electrical connector electrically couples any of the plurality of dummy dies to any of the plurality of identical chips.

19. The method of claim 15, wherein the plurality of dummy dies is blank dies free from integrated circuits therein.

20. The method of claim 15, wherein the plurality of dummy die is silicon dies free from low-k dielectric layers, metal lines, and vias therein.