Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same

• US 20130119555A1
• Filed: 03/03/2011
• Published: 05/16/2013
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Sundaram, Venkatesh, Liu, Fuhan, Tummala, Rao R., Chen, Qiao, Sukumaran, Vijay, Sridharan, Vivek
• Granted Patent: US 9,275,934 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs.

Claims

1. A microelectronic package comprising:

a plurality of through vias having walls in a glass interposer having a top portion;

a stress relief barrier on at least a portion of the top portion of the glass interposer;

a metallization seed layer on at least a portion of the stress relief layer; and

a conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

2. The microelectronic package of claim 1, wherein the stress relief barrier comprises a polymer film.

3. The microelectronic package of claim 2, wherein the polymer film comprises a thin dry film build up dielectric.

4. The microelectronic package of claim 2, wherein the polymer film is deposited as a dry film, liquid coating, or vapor phase deposition thin film.

5. The microelectronic package of claim 1, wherein the stress relief barrier has a coefficient of thermal expansion between the glass interposer and the conductor.

6. The microelectronic package of claim 1, wherein the stress relief barrier is on at least a portion of a bottom portion of the glass interposer.

7. The microelectronic package of claim 1, wherein the stress relief barrier is on at least a portion of the walls of the through vias in the glass interposer.

8. The microelectronic package of claim 1, wherein the stress relief barrier and the metallization seed layer comprise the same material.

9. The microelectronic package of claim 8, wherein the stress relief barrier and the metallization layer are selected from the group consisting of palladium, nickel, nickel allows, and copper alloys.

10. The microelectronic package of claim 1, wherein at least a portion of the remaining portion of the through vias not filled with the stress relief barrier or the metallization seed layer are filled with a filler.

11. The microelectronic package of claim 10, wherein the filler is selected from the group consisting of air, a polymer, a metal alloy, and any combination thereof.

12. The microelectronic package of claim 1, wherein the conductor forms at least one interlock.

13. A microelectronic package, comprising:

a polymer on at least a portion of a top surface of a glass interposer, wherein at least a portion of the polymer and the glass interposer are removed to form a through via;

a metallization seed layer on at least a portion of the lamination layer; and

wherein at least a portion of the through via is filled with a metal conductor forming a metallization layer, wherein a portion of the metallization layer has been selectively removed to form a metalized through package via.

14. The microelectronic package of claim 13, further comprising the polymer on at least a portion of a bottom surface of the interposer.

15. The microelectronic package of claim 13, further comprising the metallization layer on at least a portion of the side walls.

16. The microelectronic package of claim 13, wherein the polymer comprises resin-coated copper.

17. The microelectronic package of claim 13, wherein the dielectric layer comprises a compliant build-up dielectric layer.

18. A method for producing through package vias in a glass interposer, comprising:

laminating a polymer on at least a portion of a top surface of a glass interposer;

removing at least a portion of the polymer and the glass interposer to form a through via;

filling at least a portion of the through via with a metal conductor to form a metallization layer; and

selectively removing a portion of the metallization layer to form a metalized through package via.

19. The method of claim 18, further comprising depositing a metallization seed layer on at least a portion of the lamination layer prior to filling at least a portion of the through via with a metal conductor.

20. The method claim 18, further comprising laminating the polymer on at least a portion of a bottom surface of the interposer.

21. The method of claim 20, wherein laminating the polymer on at least a portion of the top surface and laminating the polymer on at least a portion of the bottom surface is performed simultaneously.

22. The method claim 18, further comprising the depositing the metallization layer on at least a portion of the side walls.

23. The method of claim 18, wherein filling at least a portion of the through via with a metal conductor to form a metallization layer further comprises closing a top portion of the through via.

24. The method claim 18, wherein the polymer comprises resin-coated copper.

25. The method claim 18, further comprising depositing a dielectric layer.

26. The method of claim 25, wherein the dielectric layer comprises a compliant buildup dielectric layer.

27. The method claim 25, wherein depositing dielectric layer comprises spin coating the dielectric layer, spraying the dielectric layer, dipping the interposer in dielectric layer, or vacuum coating the dielectric layer.

28. The method claim 18, wherein removing at least a portion of the interposer and lamination layer comprises using a laser or mechanical drilling.

29. The method claim 28, wherein the laser is a CO₂, UV or excimer laser.

30. The method of claim 18, wherein selectively removing a portion of the metallization layer to form a metalized through package via further comprises forming at least one interlock.

31-32. -32. (canceled)