CMOS IMAGE SENSOR WITH SHARED MULTIPLEXER AND METHOD OF OPERATING THE SAME

• US 20130120626A1
• Filed: 01/02/2013
• Published: 05/16/2013
• Est. Priority Date: 05/21/2009
• Status: Active Grant

• Current Assignee: PixArt Imaging Incorporated
• Original Assignee: PixArt Imaging Incorporated
• Inventors: Chan, Wei-Ting, Kao, Ming-Tsan, Hsu, En-Feng
• Granted Patent: US 9,223,444 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G06F 3/0425 using a single imaging device like a video camera for tracking the absolute position of a single or a plurality of objects with respect to an imaged reference surface, e.g. video camera imaging a display or a projection screen, a table or a wall surface, on which a computer generated image is displayed or projected tracking a projected light spot to determine a position on a display surface G06F3/0386
• CPC Class Codes: G06F 3/0428 by sensing at the edges of the touch surface the interruption of optical paths, e.g. an illumination plane, parallel to the touch surface which may be virtual sensing beam interruptions in a planar beam grid of an optical touch-screen G06F3/0421
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/779 Circuitry for scanning or addressing the pixel array

Abstract

A CMOS image sensor includes a pixel array unit, a row selection unit, and a logic circuit. The pixel array unit is used for sensing an object. The pixel array unit includes M pixels and P multiplexers and each of the M pixels is electrically connected to one of the P multiplexers, wherein M is a positive integer and P is a positive integer smaller than M. The row selection unit and the logic circuit are electrically connected to the P multiplexers. The row selection unit is used for generating a row selection signal. The logic circuit is used for determining a sensing region corresponding to the object wherein the sensing region includes N of the M pixels. Furthermore, the logic circuit controls Q multiplexers, which are electrically connected to the N pixels, to transmit the row selection signal to the N pixels.

Claims

1. A CMOS image sensor comprising:

a pixel array unit for sensing an object, the pixel array unit comprising M pixels and P multiplexers, each of the M pixels being electrically connected to one of the P multiplexers wherein M is a positive integer and P is a positive integer smaller than M;

a row selection unit, electrically connected to the P multiplexers, for generating a row selection signal; and

a logic circuit, electrically connected to the P multiplexers, for determining a sensing region corresponding to the object wherein the sensing region comprises N of the M pixels and N is a positive integer smaller than or equal to M, the logic circuit controlling Q multiplexers, which are electrically connected to the N pixels, to transmit the row selection signal to the N pixels wherein Q is a positive integer smaller than or equal to N and smaller than or equal to P.

2. The CMOS image sensor of claim 1, further comprising a read-out circuit, electrically connected to the pixel array unit, for reading signals generated by the N pixels of the sensing region.

3. The CMOS image sensor of claim 2, wherein the read-out circuit reads the signals generated by the N pixels of the sensing region in row-major order.

4. The CMOS image sensor of claim 2, wherein when the sensing region exceeds areal region of the pixel array unit, the read-out circuit adds at least one dummy pixel to the sensing region.

5. The CMOS image sensor of claim 1, wherein the sensing region is a parallelogram.

6. The CMOS image sensor of claim 1, wherein at least two of the M pixels are electrically connected to one of the P multiplexers simultaneously and the at least two pixels are located at different columns of the pixel array unit.

7. The CMOS image sensor of claim 6, wherein the at least two pixels are located at one row of the pixel array unit.

8. A method of operating a CMOS image sensor comprising steps of:

sensing an object by a pixel array unit, the pixel array unit comprising M pixels and P multiplexers, each of the M pixels being electrically connected to one of the P multiplexers wherein M is a positive integer and P is a positive integer smaller than M;

determining a sensing region corresponding to the object wherein the sensing region comprises N of the M pixels and N is a positive integer smaller than or equal to M;

generating a row selection signal; and

controlling Q multiplexers, which are electrically connected to the N pixels, to transmit the row selection signal to the N pixels wherein Q is a positive integer smaller than or equal to N and smaller than or equal to P.

9. The method of claim 8, further comprising step of reading signals generated by the N pixels of the sensing region in row-major order.

10. The method of claim 8, further comprising step of adding at least one dummy pixel to the sensing region when the sensing region exceeds a real region of the pixel array unit.

11. The method of claim 8, wherein the sensing region is a parallelogram.

12. The method of claim 8, wherein at least two of the M pixels are electrically connected to one of the P multiplexers simultaneously and the at least two pixels are located at different columns of the pixel array unit.

13. The method of claim 12, wherein the at least two pixels are located at one row of the pixel array unit.