METHOD FOR NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING READ OPERATIONS

• US 20130121072A1
• Filed: 01/07/2013
• Published: 05/16/2013
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan
• Granted Patent: US 8,705,286 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.

Claims

1. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits after a read operation;

means for reading and latching a page of data in each of a series of reading cycles, wherein said reading and latching in a current reading cycle is directed to a current page of data on a current wordline and is responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom, said reading and latching arranged to, in the current reading cycle, other than the first reading cycles, read and latch the current page while outputting a previous page read and latched in the just passed reading cycle; and

means for preemptively reading and latching the prerequisite data for the current page prior to the current reading cycle; and

wherein said means for preemptively reading and latching is arranged to, while the previous page is output, preemptively reads and latches the prerequisite data for the current page prior to the current reading cycle and to preemptively read and latch the prerequisite data for a next page that is to be read while the previous page is output.

2. The non-volatile memory device of claim 1, wherein the memory cells each stores one bit of data.

3. The non-volatile memory device of claim 1, wherein the memory cells each stores more than one bit of data and each page of memory cells on a wordline is associated with more than one page of binary data corresponding to the individual bits of each memory cell.

4. The non-volatile memory device of claim 1, wherein said means for reading and latching a page of data of the prerequisite data for the current page further comprises:

means for outputting a first flag obtained as part of the prerequisite data from said prerequisite sensing;

means for adjusting the prerequisite data responsive to the first flag; and

means for latching the adjusted prerequisite data to indicate whether corrections need to be made for the current page.

5. The non-volatile memory device of claim 4, wherein the first flag indicates whether the prerequisite page of memory cells on the adjacent wordline has been programmed with all the bits.

6. The non-volatile memory device of claim 5, wherein:

means for adjusting the prerequisite data adjusts the prerequisite data to indicate no correction is needed in response to when the first flag indicating that the adjacent wordline has not been programmed with all the bits.

7. The non-volatile memory device of claim 8, wherein:

means for adjusting the prerequisite data adjusts the prerequisite data to indicate that correction is needed in response to the first flag indicating that the adjacent wordline has been programmed with all the bits.

8. The non-volatile memory device of claim 4, wherein said means for reading and latching a page of data of a current page further comprises:

means for performing said sensing of the current page with corrections from the adjusted prerequisite data;

means for outputting a second flag obtained as part of the current page;

responsive to the second flag, means for refreshing the current page either by leaving the page unchanged, or adjusting the page to a predetermined value, or replacing with a new page obtained by repeating said sensing of the current page under another set of sensing conditions; and

means for latching the refreshed current page for outputting in the next reading cycle.

9. The non-volatile memory device of claim 8, wherein said means for reading and latching a page of data of a current page for those memory cells that needs correction as indicated by the adjusted prerequisite data is operated at a wordline voltage with a predetermined boost.

10. The non-volatile memory device of claim 8, wherein the second flag indicates whether the current page of memory cells on the current wordline has been programmed with all the bits.

11. The non-volatile memory device of claim 10, wherein:

when the second flag indicates that the adjacent wordline has been programmed with all the bits, said means for refreshing the current page leaves the current page unchanged.

12. The non-volatile memory device of claim 10, wherein:

the memory cells each stores two bits of data;

the page of memory cells is constituted from a lower-bit page and an upper-bit page; and

when the second flag indicates that the adjacent wordline has not been programmed with all the bit, and the current page being read is an upper-bit page, said means for refreshing the current page resets the current page all to a predetermined bit indicating the upper-bit page has not been programmed.

13. The non-volatile memory device of claim 10, wherein:

the memory cells each stores two bits of data;

the page of memory cells is constituted from a lower-bit page and an upper-bit page; and

when the second flag indicates that the adjacent wordline has not been programmed with all the bits, and the current page being read is a lower-bit page, said means for refreshing the current page reads the current page relative to another predetermined reference.