SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER

• US 20130121089A1
• Filed: 11/14/2012
• Published: 05/16/2013
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Park, Jungil, Lee, Chi Kong, Shin, Hyunsuk, Chen, Chih-Ching
• Granted Patent: US 8,964,498 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

Claims

1. A method for reducing an amount of peak power consumption in a device, comprising:

receiving a first signal and a second signal, wherein the first signal and the second signal are indicative of amounts of power consumption in a device;

combining the first signal with the second signal to generate a combined signal; and

shifting at least a portion of the second signal in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

2. The method of claim 1, wherein the device is a NAND flash device in a solid state drive.

3. The method of claim 1, wherein combining the first signal with the second signal comprises summing the first signal and the second signal.

4. The method of claim 1 further comprising identifying an overlapping interval, during which a first portion of the first signal overlaps in time with a second portion of the second signal.

5. The method of claim 4, wherein the first portion is indicative of data being transferred over a first channel, and the second portion is indicative of data being transferred over a second channel.

6. The method of claim 4, wherein shifting the portion comprises delaying the second portion by at least the overlapping interval.

7. The method of claim 1, wherein shifting the portion comprises interleaving first portions of the first signal with second portions of the second signal.

8. The method of claim 7, wherein the first portions and the second portions are non-uniformly shifted.

9. The method of claim 1, wherein the first signal includes a first plurality of transients, and the second signal includes a second plurality of transients.

10. The method of claim 9, wherein shifting the portion comprises delaying the second plurality of transients such that the delayed second plurality of transients and the first plurality of transients are asynchronous.

11. A system for reducing an amount of peak power consumption in a device, comprising:

a receiver configured to receive a first signal and a second signal, wherein the first signal and the second signal are indicative of amounts of power consumption in a device; and

a circuitry configured to;

combine the first signal with the second signal to generate a combined signal; and

shift at least a portion of the second signal in time, causing a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

12. The system of claim 11, wherein the device is a NAND flash device in a solid state drive.

13. The system of claim 11, wherein the circuitry combines the first signal with the second signal by summing the first signal and the second signal.

14. The system of claim 11, wherein the circuitry is further configured to identify an overlapping interval, during which a first portion of the first signal overlaps in time with a second portion of the second signal.

15. The system of claim 14, wherein the first portion is indicative of data being transferred over a first channel, and the second portion is indicative of data being transferred over a second channel.

16. The system of claim 14, wherein the circuitry shifts the portion by delaying the second portion by at least the overlapping interval.

17. The system of claim 11, wherein the circuitry shifts the portion by interleaving first portions of the first signal with second portions of the second signal.

18. The system of claim 17, wherein the first portions and the second portions are non-uniformly shifted.

19. The system of claim 11, wherein the first signal includes a first plurality of transients, and the second signal includes a second plurality of transients.

20. The system of claim 19, wherein the circuitry shifts the portion by delaying the second plurality of transients such that the delayed second plurality of transients and the first plurality of transients are asynchronous.