LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES

• US 20130124794A1
• Filed: 07/25/2011
• Published: 05/16/2013
• Est. Priority Date: 07/27/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Haas, Robert, Hu, Xiao-Yu, Pletka, Roman, Bux, Werner
• Granted Patent: US 9,256,527 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

Claims

1. A storage controller for controlling a reading and writing of data from/to a solid state memory device, comprising

a read cache for buffering address mapping information representing a subset of address mapping information stored in the memory device, which address mapping information includes a mapping of logical address information for identifying data in a requesting host to physical address information for identifying data in the memory device, and

a write cache for buffering address mapping information to be written to the memory device.

2. A storage controller according to claim 1, wherein the write cache is maintained as a unit separate from the read cache in that content buffered in the read cache is searchable independent from content buffered in the write cache and vice versa.

3. A storage controller according to claim 1, comprising one of a non-volatile memory and a volatile fail-safe memory including the write cache, and a volatile memory including the read cache.

4. A storage controller according to claim 1, comprising an allocation engine for allocating cache memory space to the read cache and to the write cache subject to one or more of a write workload and a read workload.

5. A storage controller according to claim 1, wherein an address mapping entry in the write cache includes physical address information, the logical address information associated with the physical address information, and a reference for grouping address mapping entries belonging to a common address mapping region.

6. A storage controller according to claim 5, wherein the reference corresponds to a pointer for pointing to another address mapping entry in the write cache which other address mapping entry is identified as being stored in a common page of the memory device.

7. A storage controller according to claim 6, comprising a data structure stored in the write cache including a page identifier, a counter for counting the number of entries in the write cache associated with such page identifier, and an entry pointer pointing to a write cache entry associated with such page identifier.

8. A storage system, comprising

a storage controller according to claim XX, and

a solid state memory device for storing data and for storing address mapping information for mapping logical address information for identifying data in a host accessing the storage system to physical address information for identifying data in the memory device.

9. A method for reading data from a solid state memory device, in which memory device data and mapping information for mapping physical address information for identifying data in the memory device to logical address information for identifying data in a requesting host are stored, the method comprising:

receiving logical address information associated with the data to be read,

searching the logical address information in one of a write cache for buffering address mapping information to be written to the memory device and a read cache for buffering a subset of the address mapping information stored in the memory device,

if the logical address information is not found in the cache searched, searching the logical address information in the other cache,

if the logical address information is not found in either of the write cache and the read cache, identifying and reading the physical address information associated with the logical address information by means of the mapping information stored in the memory device, and

issuing a data read operation for the physical address information identified.

10. A method according to claim 9, where the read physical address information is used to update an entry in the read cache.

11. A method according to claim 9, comprising

if the logical address information is found in the write cache identifying the physical address information associated with the logical address information from a corresponding entry in the write cache, and

issuing a data read operation for the physical address information identified.

12. A method according to claim 9, comprising

if the logical address information is found in the read cache identifying the physical address information associated with the logical address information from a corresponding entry in the read cache, and

issuing a data read operation for the physical address information identified.

17. A computer program product comprising a computer readable medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to perform a method according to claim 9.

13. A method for writing data to a solid state memory device, in which memory device data and mapping information for mapping logical address information identifying data in a request to physical address information for identifying data in the memory device are stored, the method comprising:

receiving the data and logical address information associated with the data,

writing the data to a location of the memory device identified by physical address information,

searching the logical address information in a write cache dedicated for buffering address mapping information to be written to the memory device, and

if the logical address information is not found in the write cache, adding an address mapping entry to the write cache comprising a mapping of the logical address.

14. A method according to claim 13, comprising if the logical address information is found in the write cache updating the corresponding address mapping entry in the write cache with the physical address information newly associated with the data.

15. A method according to claim 13, comprising searching the logical address information in a read cache for buffering address mapping information representing a subset of the address mapping information stored in the memory device, and if the logical address information is found in the read cache updating the corresponding address mapping entry in the read cache with the physical address information newly associated with the data.

16. A method according to claim 15, comprising searching the logical address information in the read cache at a time the write cache is updated.