LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES
First Claim
1. A storage controller for controlling a reading and writing of data from/to a solid state memory device, comprisinga read cache for buffering address mapping information representing a subset of address mapping information stored in the memory device, which address mapping information includes a mapping of logical address information for identifying data in a requesting host to physical address information for identifying data in the memory device, anda write cache for buffering address mapping information to be written to the memory device.
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Abstract
The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.
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Citations
17 Claims
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1. A storage controller for controlling a reading and writing of data from/to a solid state memory device, comprising
a read cache for buffering address mapping information representing a subset of address mapping information stored in the memory device, which address mapping information includes a mapping of logical address information for identifying data in a requesting host to physical address information for identifying data in the memory device, and a write cache for buffering address mapping information to be written to the memory device.
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8. A storage system, comprising
a storage controller according to claim XX, and a solid state memory device for storing data and for storing address mapping information for mapping logical address information for identifying data in a host accessing the storage system to physical address information for identifying data in the memory device.
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9. A method for reading data from a solid state memory device, in which memory device data and mapping information for mapping physical address information for identifying data in the memory device to logical address information for identifying data in a requesting host are stored, the method comprising:
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receiving logical address information associated with the data to be read, searching the logical address information in one of a write cache for buffering address mapping information to be written to the memory device and a read cache for buffering a subset of the address mapping information stored in the memory device, if the logical address information is not found in the cache searched, searching the logical address information in the other cache, if the logical address information is not found in either of the write cache and the read cache, identifying and reading the physical address information associated with the logical address information by means of the mapping information stored in the memory device, and issuing a data read operation for the physical address information identified. - View Dependent Claims (10, 11, 12, 17)
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13. A method for writing data to a solid state memory device, in which memory device data and mapping information for mapping logical address information identifying data in a request to physical address information for identifying data in the memory device are stored, the method comprising:
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receiving the data and logical address information associated with the data, writing the data to a location of the memory device identified by physical address information, searching the logical address information in a write cache dedicated for buffering address mapping information to be written to the memory device, and if the logical address information is not found in the write cache, adding an address mapping entry to the write cache comprising a mapping of the logical address. - View Dependent Claims (14, 15, 16)
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Specification