DYNAMIC LDPC CODE RATE SOLUTION

• US 20130124945A1
• Filed: 11/15/2012
• Published: 05/16/2013
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: HU, Xinde, Barndt, Richard D.
• Granted Patent: US 8,762,798 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

Abstract

The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate.

Claims

1. A method for adjusting a code rate in a solid-state drive, the method comprising:

performing a first plurality of memory operations on a flash memory device using a first code rate;

monitoring an operating condition associated with one or more memory units of the flash memory device for a trigger event;

adjusting, on the trigger event, the first code rate in accordance with the operating condition to produce a second code rate; and

performing a second plurality of memory operations on the flash memory device using the second code rate.

2. The method of claim 1, wherein the operating condition comprises a number of program/erase (P/E) cycles.

3. The method of claim 2, wherein the trigger event comprises the number of P/E cycles satisfying a threshold number of P/E cycles.

4. The method of claim 2, further comprising:

determining, on the trigger event, the second code rate by indexing a lookup table by a current range of P/E cycles.

5. The method of claim 1, wherein the operating condition comprises an error rate.

6. The method of claim 5, wherein the trigger event comprises the error rate satisfying a threshold error rate.

7. The method of claim 5, further comprising:

determining, on the trigger event, the second code rate by indexing a lookup table by a current range of error rates.

8. The method of claim 1, further comprising:

storing host data in a first plurality of memory units at the first code rate; and

storing host data in a second plurality of memory units at the second code rate.

9. The method of claim 8, further comprising:

decoding host data from the first plurality of memory units at the first code rate; and

decoding host data from the second plurality of memory units at the second code rate.

10. The method of claim 1, further comprising:

storing a code rate flag in connection with encoding host data for the one or more memory units;

determining, in connection with reading the one or more memory units, a decoding code rate based on the stored code rate flag for the one or more memory units; and

decoding host data for the one or memory units based on the determined decoding code rate.

11. The method of claim 1, wherein adjusting the first code rate comprises:

reducing the first code rate by an amount predetermined to sustain a raw read error rate associated with one or more memory blocks below a predetermined threshold for a predetermined number of P/E cycles.

12. The method of claim 1, wherein the second code rate has a lower code rate value than the first code rate.

13. The method of claim 1, wherein adjusting the first code rate modifies an amount of storage available for user data in future operations.

14. The method of claim 1, wherein the code rate is a LDPC code rate.

15. A machine-readable medium having instructions stored thereon that, when executed, cause a machine to perform a method for adjusting a code rate in a solid state drive, the method comprising:

receiving a first quantity of host data;

encoding, for storage in one or more memory units, a first quantity of host data at a first code rate, the first code rate corresponding to a predetermined code rate value;

monitoring one or more operating conditions associated with the one or more memory units for a trigger event;

adjusting, on a predetermined trigger event, the code rate value;

receiving a second quantity of host data; and

encoding, for storage in the one or more memory units, a second quantity of host data at a second code rate.

16. The machine readable medium of claim 15, wherein adjusting the code rate value comprises:

adjusting the code rate value by an amount sufficient to reduce, below a predetermined threshold, a read error rate produced in connection with future memory operations.

17. The machine readable medium of claim 15, wherein the one or more operating conditions comprise an error rate or a number of program/erase cycles, and wherein the trigger event comprises a threshold error rate or threshold program/erase cycle.

18. The machine readable medium of claim 15, further comprising:

storing host data in a first plurality of memory units at the first code rate; and

storing host data in a second plurality of memory units at the second code rate.

19. The machine readable medium of claim 15, further comprising:

decoding host data from the first plurality of memory units at the first code rate; and

decoding host data from the second plurality of memory units at the second code rate.

20. The machine readable medium of claim 15, further comprising:

storing a code rate flag in connection with encoding host data for the one or more memory units;

determining, in connection with reading the one or more memory units, a decoding code rate based on the stored code rate flag for the one or more memory units; and

decoding host data from the one or memory units based on the determined decoding code rate.

21. The machine readable medium of claim 15, wherein the code rate is a LDPC code rate.

22. A system, comprising:

a flash controller;

one or more flash memory devices; and

one or more embedded memories associated with the controller, the memories having instructions stored thereon that, when executed, cause the flash controller to;

monitor one or more operating conditions associated with the one or more flash memory devices for one or more trigger events; and

adjust, on a predetermined trigger event, a LDPC code rate used in current memory operations performed by the flash controller by an amount sufficient to reduce, below a predetermined threshold, a read error rate produced in connection with future memory operations.