INTEGRATED CIRCUITS WITH ELECTRICAL FUSES AND METHODS OF FORMING THE SAME
First Claim
1. A method of forming an integrated circuit, the method comprising:
- forming at least one transistor over a substrate, wherein forming the at least one transistor comprises;
forming a gate dielectric structure over a substrate;
forming a work-function metallic layer over the gate dielectric structure;
forming a conductive layer over the work-function metallic layer; and
forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure; and
forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises;
forming a first semiconductor layer over the substrate; and
forming a first silicide layer on the first semiconductor layer.
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Accused Products
Abstract
A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
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Citations
20 Claims
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1. A method of forming an integrated circuit, the method comprising:
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forming at least one transistor over a substrate, wherein forming the at least one transistor comprises; forming a gate dielectric structure over a substrate; forming a work-function metallic layer over the gate dielectric structure; forming a conductive layer over the work-function metallic layer; and forming a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure; and forming at least one electrical fuse over the substrate, wherein forming the at least one electrical fuse comprises; forming a first semiconductor layer over the substrate; and forming a first silicide layer on the first semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming an integrated circuit, the method comprising:
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forming a first semiconductor layer in a transistor region over a substrate and a second semiconductor layer in a fuse region over the substrate; forming a first silicide layer on the first semiconductor layer and a second silicide layer on the second semiconductor layer; forming a dielectric layer around the first and second semiconductor layers, exposing the first and second silicide layers; forming a cap layer covering the second silicide layer and exposing the first silicide layer; removing the first silicide layer and the first semiconductor layer to form a first opening that is left by the removed first silicide layer and the removed first semiconductor layer; and sequentially forming a work-function metallic layer and a conductive layer in the first opening. - View Dependent Claims (12, 13, 14, 15)
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16. An integrated circuit comprising:
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at least one transistor and at least one electrical fuse disposed over the substrate, wherein the at least one transistor comprises; a gate dielectric structure disposed over the substrate; a work-function metallic layer disposed over the gate dielectric structure; a conductive layer disposed over the work-function metallic layer; and a source/drain (S/D) region disposed adjacent to each sidewall of the gate dielectric structure; and wherein the at least one electrical fuse comprises; a first semiconductor layer over the substrate; and a first silicide layer on the first semiconductor layer. - View Dependent Claims (17, 18, 19, 20)
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Specification