METHOD FOR PRODUCING A GRAPHENE SHEET ON A PLATINUM SILICIDE, STRUCTURES OBTAINED USING SAID METHOD AND USES THEREOF

• US 20130127023A1
• Filed: 11/06/2012
• Published: 05/23/2013
• Est. Priority Date: 11/07/2011
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Zenasni, Aziz
• Granted Patent: US 9,159,550 B2
• Time in Patent Office: Days
• US Class Current: 257/635
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: C01B 32/184 Preparation
• CPC Class Codes: C23C 10/52 more than one element being diffused in one step
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/0281 of metallic sub-layers C23C16/029 takes precedence
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: C23C 28/046 with at least one amorphous inorganic material layer, e.g. DLC, a-C:H, a-C:Me, the layer being doped or not
• CPC Class Codes: C23C 28/322 only coatings of metal elements only
• CPC Class Codes: C23C 28/343 with at least one DLC or an amorphous carbon based layer, the layer being doped or not
• CPC Class Codes: C23C 28/345 with at least one oxide layer
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Abstract

The invention relates to a method for producing a graphene sheet on a platinum silicide, wherein the platinum silicide is in the form of a layer or a plurality of pins.

This method comprises:

a) producing a stack by (i) depositing a layer C1 of a diffusion barrier material on a substrate; (ii) depositing, on the layer C1, a layer C2 of a carbon-containing material, wherein said carbon-containing material optionally comprises silicon; (iii) depositing, on the layer C2, a layer C3 of platinum; (iv) depositing a layer C4 of a material of formula Si_aC_bH_c on the layer C3 if the carbon-containing material of the layer C2 is free from silicon; and

b) heat-treating the stack obtained at step a).

It also relates to structures obtained using this method and the uses of these structures.

Applications: manufacture of micro- and nanoelectronic devices, micro- and nanoelectromechanical devices, etc.

Claims

1. A method for producing a graphene sheet on a platinum silicide of formula Pt_xSi, wherein x is a number greater than or equal to two, comprising:

a) producing a stack by;

i) depositing a layer C1 of a diffusion barrier material on a substrate;

ii) depositing, on the layer C1, a layer C2 of a carbon-containing material comprising silicon;

iii) depositing, on the layer C2, a layer C3 of platinum; and

b) heat-treating the stack obtained at a);

and wherein the ratio of the number of platinum atoms found in the layer C3 with respect to the number of silicon atoms found in the layer C2 is greater than or equal to two.

2. The method of claim 1, wherein the diffusion barrier material is silicon dioxide.

3. The method of claim 1, wherein the carbon-containing material comprising silicon is selected from the group consisting of amorphous carbon-containing materials.

4. The method of claim 3, wherein the amorphous carbon-containing material comprising silicon comprises 20% or more by mass of silicon.

5. The method of claim 4, wherein the amorphous carbon-containing material comprising silicon comprises 40% or more by mass of silicon.

6. The method of claim 4, wherein the amorphous carbon-containing material comprising silicon is a hydrogenated amorphous silicon carbide of formula a-Si_α

C_β

;

H, wherein α and

β

, which are identical or different, are numbers greater than 0.

7. The method of claim 6, wherein the formula of the hydrogenated amorphous silicon carbide is a-Si_α

C_β

;

H wherein α and

β

are both equal to 1.

8. The method of claim 1, wherein the layer C2 is deposited by plasma-enhanced chemical vapor deposition.

9. The method of claim 1, wherein the layer C3 is deposited by physical vapor deposition, at a temperature ranging from 20 to 30°

C.

10. The method of claim 1, wherein the heat treatment is carried out at a temperature ranging from 750°

C. to 850°

C., in a neutral atmosphere.

11. The method of claim 1, wherein the heat treatment comprises:

a first heat treatment carried out at a temperature ranging from 250°

C. to 350°

C., in a neutral atmosphere; and

a second heat treatment carried out at a temperature ranging from 750°

C. to 850°

C., in a neutral atmosphere.

26. A method for manufacturing a device selected from the group consisting of microelectronic, nanoelectronic, microelectromechanical and nanoelectromechanical devices, comprising the implementation of the method of claim 1.

12. A method for producing a graphene sheet on a platinum silicide of formula PtxSi, wherein x is a number greater than or equal to two, comprising:

a) producing a stack by;

i) depositing a layer C1 of a diffusion barrier material on a substrate;

ii) depositing, on the layer C1, a layer C2 of a carbon-containing material free from silicon;

iii) depositing, on the layer C2, a layer C3 of platinum;

iv) depositing, on the layer C3, a layer C4 of a material of formula Si_aC_bH_c wherein a is greater than 0 whereas b and c, which are identical or different, are greater than or equal to 0; and

b) heat-treating the stack obtained at a);

and wherein the ratio of the number of platinum atoms found in the layer C3 with respect to the number of silicon atoms found in the layer C4 is greater than or equal to two.

13. The method of claim 12, wherein the diffusion barrier material is silicon dioxide.

14. The method of claim 12, wherein the carbon-containing material free from silicon is selected from the group consisting of amorphous carbon-containing materials free from silicon.

15. The method of claim 14, wherein the amorphous carbon-containing material free from silicon is hydrogenated amorphous carbon a-C:

H.

16. The method of claim 12, wherein the material having the formula Si_aC_bH_c is hydrogenated amorphous silicon a-Si:

H.

17. The method of claim 12, wherein the layer C2 is deposited by plasma-enhanced chemical vapor deposition.

18. The method of claim 12, wherein the layer C3 is deposited by physical vapor deposition, at a temperature ranging from 20°

C. to 30°

C.

19. The method of claim 16, wherein the layer of a-Si:

H is deposited by plasma-enhanced chemical vapor deposition.

20. The method of claim 12, wherein the heat treatment is carried out at a temperature ranging from 750°

C. to 850°

C., in a neutral atmosphere.

21. The method of claim 12, wherein the heat treatment comprises:

a first heat treatment carried out at a temperature ranging from 250°

C. to 350°

C., in a neutral atmosphere; and

a second heat treatment carried out at a temperature ranging from 750°

C. to 850°

C., in a neutral atmosphere.

27. A method for manufacturing a device selected from the group consisting of microelectronic, nanoelectronic, microelectromechanical and nanoelectromechanical devices, comprising the implementation of the method of claim 12.

22. A structure, comprising:

a substrate;

a layer C1 of a diffusion barrier material covering the substrate;

a platinum silicide covering the layer C1, wherein the formula of the platinum silicide is Pt_xSi where x is a number greater than or equal to two and wherein the platinum silicide is in the form of a layer or spaced pins; and

a graphene sheet covering the layer of pins of the platinum silicide.

23. The structure of claim 22, wherein the diffusion barrier material is silicon dioxide.

24. The structure of claim 22, wherein the graphene sheet comprises at least two layers of graphene.

25. A structure, comprising a graphene sheet having two faces, wherein the graphene sheet comprises on one of its faces a platinum silicide of formula Pt_xSi where x is a number greater than or equal to two, and the platinum silicide is in the form of a layer or a plurality of spaced pins.