AMORPHOUS OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR FABRICATION METHOD

• US 20130127694A1
• Filed: 11/18/2011
• Published: 05/23/2013
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Kim, Cheonghong, Chang, Tallis Young, Hong, John Hyunchul
• Granted Patent: US 9,379,254 B2
• Time in Patent Office: Days
• US Class Current: 345/82
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

This disclosure provides systems, methods and apparatus for fabricating thin film transistor (TFT) devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. Metal cations are implanted in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The metal cation implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.

Claims

1. A method comprising:

providing a substrate, the substrate having a surface, the surface including a source area, a drain area, and a channel area, the substrate including an oxide semiconductor layer on the surface of the substrate, and a mask on the oxide semiconductor layer overlying the channel area of the substrate; and

implanting metal cations in the oxide semiconductor layer overlying the source area and the drain area of the substrate to form doped n-type oxide semiconductor layers.

2. The method of claim 1, wherein the mask includes a metal gate for a thin film transistor (TFT).

3. The method of claim 1, wherein the metal cations are cations of a constituent metal of the oxide semiconductor layer.

4. The method of claim 1, wherein the oxide semiconductor layer includes one or more of indium (In), gallium (Ga), zinc (Zn), hafnium (Hf), and tin (Sn).

5. The method of claim 1, wherein the metal cations include one or more of indium cations (In⁺), gallium cations (Ga⁺), zinc cations (Zn⁺), hafnium cations (Hf⁺), and tin cations (Sn⁺).

6. The method of claim 1, further comprising forming a first dielectric layer on the oxide semiconductor layer overlying the channel area, and forming a first metal layer on the first dielectric layer.

7. The method of claim 6, wherein the mask includes the first metal layer.

8. The method of claim 6, further comprising:

forming a second dielectric layer on the first metal layer and the doped n-type oxide semiconductor layers;

removing portions of the second dielectric layer to expose the doped n-type oxide semiconductor layer overlying the source area of the substrate and the doped n-type oxide semiconductor layer overlying the drain area of the substrate; and

forming a first and a second contact, the first contact contacting the doped n-type oxide semiconductor layer overlying the source area of the substrate, and the second contact contacting the doped n-type oxide semiconductor layer overlying the drain area of the substrate.

9. The method of claim 6, further comprising:

forming a second dielectric layer on the first metal layer and on the oxide semiconductor layer overlying the source area and the drain area of the substrate; and

etching the second dielectric layer to form dielectric sidewalls associated with the first metal layer and the first dielectric layer.

10. The method of claim 1, wherein the metal cations are implanted to a concentration in the oxide semiconductor layer overlying the source area and the drain area of the substrate of greater than about 10¹⁹ atoms/cm³.

11. The method of claim 1, wherein the oxide semiconductor layer is about 10 to 100 nanometers thick.

12. The method of claim 1, further comprising implanting first ions in at least a region of the oxide semiconductor layer overlying the channel area.

13. The method of claim 12, wherein the first ions are metal cations.

14. The method of claim 12, wherein the first ions are implanted using a dose of at between about 10¹² atoms/cm² and 10²⁰ atoms/cm².

15. A device fabricated in accordance with the method of claim 1.

16. An apparatus comprising:

a substrate including a surface;

an oxide semiconductor layer on the substrate surface, the oxide semiconductor layer including a channel region, a source region, and a drain region, the source region and the drain region of the oxide semiconductor layer being doped n-type oxide semiconductor layers implanted with metal cations to a concentration of greater than about 10¹⁹ atoms/cm³;

a first dielectric layer on the channel region of the oxide semiconductor layer; and

a first metal layer on the first dielectric layer.

17. The apparatus of claim 16, wherein the metal cations are cations of a constituent metal of the oxide semiconductor layer.

18. The apparatus of claim 16, wherein the oxide semiconductor layer includes one or more of indium (In), gallium (Ga), zinc (Zn), hafnium (Hf), and tin (Sn).

19. The apparatus of claim 16, wherein the metal cations include one or more of indium cations (In+), gallium cations (Ga+), zinc cations (Zn+), hafnium cations (Hf+), and tin cations (Sn+).

20. The apparatus of claim 16, further comprising a first contact contacting the source region;

and a second contact contacting the drain region.

21. The apparatus of claim 16, further comprising:

a dielectric sidewall on both sides of the first dielectric layer and on both sides of the first metal layer, a first dielectric sidewall and a second dielectric sidewall overlying portions of the channel region of the oxide semiconductor layer.

22. The apparatus of claim 16, further comprising:

a second dielectric layer, wherein the second dielectric layer is on the first metal layer, the source region of the oxide semiconductor layer, and the drain region of the oxide semiconductor layer.

23. The apparatus of claim 16, wherein the substrate includes a glass substrate.

24. The apparatus of claim 16, further comprising:

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

25. The apparatus of claim 24, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

26. The apparatus of claim 24, further comprising:

an image source module configured to send the image data to the processor, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.

27. The apparatus of claim 24, further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

28. The apparatus of claim 24, wherein the display is a liquid crystal display or an organic light-emitting diode display.