HYBRID READ SCHEME FOR SPIN TORQUE MRAM

• US 20130128657A1
• Filed: 10/02/2012
• Published: 05/23/2013
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Alam, Syed M., Andre, Thomas, Subramanian, Chitra
• Granted Patent: US 9,183,911 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value

Abstract

A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.

Claims

1. A method of reading data from a plurality of bits in a spin-torque magnetoreistive memory array, the method comprising:

completing at least one referenced read operation and at least one self-referenced read operation.

2. The method of claim 1 wherein the referenced read operation is completed prior to the self referenced read operation.

3. The method of claim 1 wherein the referenced read operation occurs simultaneously with at least a portion of the self referenced read operation.

4. The method of claim 1 wherein the self-referenced read operation is a destructive self-referenced read operation and the destructive self-referenced read operation comprises for each of the bits:

applying a read bias voltage across the bit;

converting a first current through the bit to a gate voltage;

storing the gate voltage;

applying a second current to reset the bit to a predetermined state;

reapplying the read bias voltage across the bit;

determine a third current through the bit;

generate an evaluation voltage by comparing the sum of the third current and an offset current with the first current; and

if the evaluation voltage is less than the stored gate voltage, apply a fourth current to write the bit opposite to the predetermined state.

5. The method of claim 1 wherein at least one of an average low bit resistance or an average high bit resistance of the bits is used for the referenced read operation.

6. The method of claim 1 wherein the referenced read operation uses a programmable current or a programmable voltage for reference.

7. The method of claim 1 wherein the referenced read operation comprises for each of the bits:

applying a read bias voltage across the bit;

converting a first current through the bit to a gate voltage;

storing the gate voltage;

generating an output voltage using an average resistance for one of low states or high states; and

comparing the output voltage with the stored gate voltage to determine the state of the bit.

8. A method of reading data from a plurality of bits in a spin-torque magnetoreistive memory array, the method comprising:

performing at least one referenced read operation of the bits to read at least a portion of the bits; and

performing a self-referenced read operation of any of the bits not successfully read by the referenced read operation.

9. The method of claim 8 further comprising completing the referenced read operation of the bits prior to the self-referenced read operation and preventing the self-referenced read operation to the bits successfully read by the referenced read operation.

10. The method of claim 8 further comprising completing the referenced read operation in parallel to a portion of the self-reference read operation and preventing another portion of the self-referenced read operation to the bits successfully read by the referenced read operation.

11. The method of claim 8 wherein the self-referenced read is a destructive self-referenced read operation and the destructive self-referenced read further comprises for each of the bits:

applying a read bias voltage across the bit;

converting a first current through the bit to a gate voltage;

storing the gate voltage;

applying a second current to reset the bit to a predetermined state;

reapplying the read bias voltage across the bit;

determine a third current through the bit;

generate an evaluation voltage by comparing the sum of the first current with the third current and an offset current; and

if the evaluation voltage is less than the stored gate voltage, apply a fourth current to write the bit opposite to the predetermined state.

12. The method of claim 8 wherein at least one of an average low bit resistance or an average high bit resistance of the bits is used for the referenced read operation.

13. The method of claim 8 wherein the referenced read operation uses a programmable current or a programmable voltage for reference

14. The method of claim 8 wherein the referenced read operation comprises for each of the bits:

applying a read bias voltage across the bit;

converting a first current through the bit to a gate voltage;

storing the gate voltage;

generating an output voltage using an average resistance for one of low states or high states; and

comparing the output voltage with the stored gate voltage to determine the state of the bit.

15. A circuit for reading data from a plurality of bits in a spin-torque magnetoresistive memory array, the circuit comprising:

first circuitry coupled to the array and configured to perform a referenced read of the bits; and

second circuitry coupled both to the array and the first circuitry, and configured to perform a self-referenced read of the bits.

16. The circuit of claim 15 wherein the first circuitry is configured to complete the referenced read of the bits prior to the second circuitry performing the self-referenced read of the bits, and the second circuit is configured to read only the bits not successfully read by the first circuit.

17. The circuit of claim 15 wherein the first circuit is configured to perform the referenced read operation and the second circuit is configured to perform the self-referenced read with at least portions of each in parallel and to prevent a portion of the self-referenced read operation of the bits successfully read by the referenced read operation.

18. The circuit of claim 15 wherein the second circuit is configured to, for each of the bits:

apply a read bias voltage across the bit;

convert a first current through the bit to a gate voltage;

store the gate voltage;

apply a second current to reset the bit to a predetermined state;

reapply the read bias voltage across the bit;

determine a third current through the bit;

generate an evaluation voltage by comparing the sum of the first current with the third current and an offset current; and

if the evaluation voltage is less than the stored gate voltage, apply a fourth current to write the bit opposite to the predetermined state.

19. The circuit of claim 15 wherein the first circuit is configured to consider at least one of an average low bit resistance or an average high bit resistance of the bits for the referenced read operation.

20. The circuit of claim 15 wherein the first circuit is configured to consider a programmable current or a programmable voltage for reference.

21. The circuit of claim 15 wherein the first circuit is configured to, for each of the bits:

apply a read bias voltage across the bit;

convert a first current through the bit to a gate voltage;

store the gate voltage;

generate an output voltage using an average resistance for one of low states or high states; and

compare the output voltage with the stored gate voltage to determine the state of the bit.