NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM AND CONTROLLER OPERATING METHOD
First Claim
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1. A nonvolatile memory device, comprising:
- a first plane configured to perform a first operation directed to a first memory cell array in response to a first command received from a controller;
a second plane configured to perform a second operation directed to a second memory cell array physically separate from the first memory cell array in response to a second command received from the controller; and
a data input/output (I/O) circuit that transfers read data to the controller via a common data bus obtained from at least one of the first memory cell array and the second memory cell array in response to a read command, that transfers program data received from the controller via the common data bus to at least one of the first memory cell array and the second memory cell array in response to a program command, and that provides a ready/busy signal indicating one of an idle state and a busy state,wherein the state of the ready/busy signal determines whether the first command and the second command are executed.
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Abstract
An operating method for a memory system provides a ready/busy signal from a nonvolatile memory device indicating an idle state or a busy state to a controller. The controller generates a next command but transfers the next command to the nonvolatile memory device in response to the ready/busy signal and the idle verse busy state of a target plane among multiple planes of the nonvolatile memory device.
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Citations
20 Claims
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1. A nonvolatile memory device, comprising:
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a first plane configured to perform a first operation directed to a first memory cell array in response to a first command received from a controller; a second plane configured to perform a second operation directed to a second memory cell array physically separate from the first memory cell array in response to a second command received from the controller; and a data input/output (I/O) circuit that transfers read data to the controller via a common data bus obtained from at least one of the first memory cell array and the second memory cell array in response to a read command, that transfers program data received from the controller via the common data bus to at least one of the first memory cell array and the second memory cell array in response to a program command, and that provides a ready/busy signal indicating one of an idle state and a busy state, wherein the state of the ready/busy signal determines whether the first command and the second command are executed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An operating method for a controller that controls a nonvolatile memory device including a plurality of planes, each plane being respectively and independently configured to perform an operation relative to other planes in the plurality of planes, the operating method comprising:
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generating a next command directed to a target plane among the plurality of planes; performing a status read operation to determine whether the target plane is in an idle state or a busy state; if the target state is in the idle state, transferring the next command to the nonvolatile memory device for execution, and if the target state is in the busy state determining a priority for the next command. - View Dependent Claims (11, 12)
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13. An operating method for a memory system including a controller and a nonvolatile memory device including first and second planes being respectively and independently configured to perform an operation relative, the operating method comprising:
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providing a ready/busy signal from the nonvolatile memory device indicating one of an idle state and a busy state for the nonvolatile memory device; in the controller, generating a next command indicating a first operation directed to the first plane; and
then,if the ready/busy indicates the idle state, performing a status read operation to determine whether the first plane is in the idle state, and if the first plane is in the idle state immediately transferring the next command to the nonvolatile memory device, otherwise waiting to transfer the next command to the nonvolatile memory. - View Dependent Claims (14, 15, 16)
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17. A memory system comprising:
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a controller and a nonvolatile memory device controlled in its operation by the controller, wherein the nonvolatile memory comprises; a first plane configured to perform a first operation directed to a first memory cell array in response to a first command received from the controller, a second plane configured to perform a second operation directed to a second memory cell array physically separate from the first memory cell array in response to a second command received from the controller; and a data input/output (I/O) circuit that transfers read data to the controller via a common data bus obtained from at least one of the first memory cell array and the second memory cell array in response to a read command, that transfers program data received from the controller via the common data bus to at least one of the first memory cell array and the second memory cell array in response to a program command, and that provides a ready/busy signal indicating one of an idle state and a busy state, wherein the state of the ready/busy signal determines whether the first command and the second command are executed. - View Dependent Claims (18, 19, 20)
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Specification