REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS

• US 20130130498A1
• Filed: 12/18/2012
• Published: 05/23/2013
• Est. Priority Date: 03/31/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Feustel, Frank, Werner, Thomas, Grillberger, Michael, Frohberg, Kai
• Application Number:
  US13/718,644
• Publication Number:
  US 20130130498A1
• Time in Patent Office: Days
• US Class Current: 438/675
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process.

Claims

1-9. -9. (canceled)

10. A method, comprising:

forming a via opening in a first dielectric material of a metallization layer of a semiconductor device;

forming a second dielectric material above said first dielectric material, said second dielectric material filling said via opening;

forming a trench in said second dielectric material so as to connect to said via opening; and

filling said trench and said via opening with a metal in a common fill process.

11. The method of claim 10, wherein forming said trench comprises etching said second dielectric material and using said first dielectric material as an etch stop.

12. The method of claim 10, further comprising forming a conductive barrier layer in said via opening and said trench prior to performing said common fill process.

13. The method of claim 10, wherein forming said second dielectric material comprises applying a low k dielectric material by performing a spin-on process.

14. The method of claim 10, further comprising forming an etch stop layer on said first dielectric material and within said via opening prior to forming said second dielectric material.

15. The method of claim 14, further comprising removing said etch stop layer from a bottom of said via opening after forming said trench.

16. The method of claim 14, wherein said via opening is formed so as to extend to a surface of a metal region located below said first dielectric material prior to forming said etch stop layer.

17. The method of claim 16, further comprising removing said etch stop layer from said surface of said metal region prior to performing said common fill process.

22. The method of claim 10, wherein forming said trench comprises removing said second dielectric material from said via opening.

18-21. -21. (canceled)

23. A method, comprising:

forming an etch stop layer above a contact region of a semiconductor device;

forming a first dielectric layer above said etch stop layer;

forming a via opening in said first dielectric layer;

after forming said via opening, forming a second dielectric layer above said first dielectric layer;

forming a trench opening in said second dielectric layer and above said via opening; and

performing a common deposition process to completely fill said trench opening and said via opening with a conductive contact material.

24. The method of claim 23, wherein forming said second dielectric layer comprises forming a material layer comprising a low-k dielectric material, said material layer filling said via opening and covering said first dielectric layer.

25. The method of claim 23, wherein forming said trench opening comprises forming a portion of said trench opening in said first dielectric layer.

26. The method of claim 23, wherein forming said trench opening comprises exposing said contact region.

27. The method of claim 26, wherein exposing said contact region comprises removing said etch stop layer at a bottom of via opening from above said contact region.

28. The method of claim 23, further comprising forming a third dielectric layer inside of said via opening and above said first dielectric layer prior to forming said second dielectric layer.

29. The method of claim 28, further comprising using said third dielectric layer as an etch stop layer when forming said trench opening.

30. The method of claim 29, further comprising removing said etch stop layer from a bottom of said via opening prior to forming said third dielectric layer.

31. The method of claim 29, wherein forming said trench opening comprises removing said third dielectric layer from a bottom of said via opening and from above said first dielectric layer at a bottom of said trench opening.

32. The method of claim 31, further comprising removing at least a portion of said third dielectric layer from sidewalls of said via opening.

33. The method of claim 23, further comprising forming a barrier layer on exposed surface portions of said trench opening and said via opening prior to performing said common deposition process.