Method and Apparatus for Scalable Low Latency Solid State Drive Interface

• US 20130132643A1
• Filed: 04/30/2012
• Published: 05/23/2013
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Mason Licensing LLC (IP Edge LLC)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Huang, Yiren
• Granted Patent: US 9,767,058 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.

Claims

1. A solid state drive (SSD) apparatus, comprising:

a plurality of solid state drives;

a channel-interleaved interface operably coupled to the solid state drives; and

a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.

2. The SSD apparatus of claim 1, wherein the channel-interleaved interface utilizes a data frame format including a frame header, frame data, and a frame cyclic redundancy check (CRC).

3. The SSD apparatus of claim 1, wherein the channel-interleaved interface interleaves a read command between portions of write commands.

4. The SSD apparatus of claim 1, wherein the channel-interleaved interface issues write commands in multiple bursts.

5. The SSD apparatus of claim 1, wherein the PCIe bridge is operably coupled to a PCIe bridge controller.

6. The SSD apparatus of claim 1, wherein a plurality of PCIe bridges are operably coupled to the channel-interleaved interface.

7. The SSD apparatus of claim 6, wherein the PCIe bridges are operably coupled to a blade motherboard.

8. The SSD apparatus of claim 1, wherein the channel-interleaved interface comprises a fabric switch.

9. The SSD apparatus of claim 1, wherein the channel-interleaved interface is operably coupled to a fiber channel network connection.

10. The SSD apparatus of claim 1, wherein the channel-interleaved interface is operably coupled to a network connection.

11. A solid state drive (SSD) apparatus, comprising:

a plurality of solid state drives;

a channel-interleaved interface operably coupled to the solid state drives; and

a plurality of Peripheral Component Interconnect Express (PCIe) bridges operably coupled to the channel-interleaved interface, each of the PCIe bridges configured to exchange data with each of the solid state drives through the channel-interleaved interface.

12. The SSD apparatus of claim 11, wherein the channel-interleaved interface inserts a read command after a first portion of a write command and before a second portion of the write command.

13. The SSD apparatus of claim 11, wherein the channel-interleaved interface sends write commands to the solid state drives in discrete segment bursts.

14. The SSD apparatus of claim 11, wherein the plurality of PCIe bridges are operably coupled to a blade motherboard.

15. The SSD apparatus of claim 11, wherein the channel-interleaved interface comprises a fabric switch.

16. The SSD apparatus of claim 11, wherein the channel-interleaved interface is configured to exchange with the solid state drives data frames having a frame header.

17. The SSD apparatus of claim 11, wherein the channel-interleaved interface is configured to exchange with the solid state drives data frames having a frame cyclic redundancy check (CRC) frame.

18. The SSD apparatus of claim 11, wherein the channel-interleaved interface is operably coupled to a fiber channel network connection.

19. The SSD apparatus of claim 11, wherein the channel-interleaved interface is operably coupled to a network connection.

20. A method of accessing data stored in a solid state drive, the method comprising:

interleaving a read command with a first portion of a write data command and a second portion of the write data command to form an interleaved command;

sending the interleaved command to the solid state drive via an interleaved channel-based interface; and

receiving the data from the solid state drive in response to the read command in the interleaved command.

21. The method of claim 20, further comprising formatting a data frame to include a frame header.

22. The method of claim 21, further comprising formatting the data frame to include a cyclic redundancy check (CRC) header.

23. The method of claim 22, further comprising formatting the data into data frames disposed between the frame header and the CRC header.

24. The method of claim 20, further comprising sending the data received from the solid state drive to a PCIe bridge.

25. The method of claim 20, further comprising accessing a fiber channel network connection through the interleaved channel-based interface.

26. The method of claim 20, further comprising accessing a network connection through the interleaved channel-based interface.