ADAPTIVE DATA PREFETCH

• US 20130132680A1
• Filed: 11/20/2011
• Published: 05/23/2013
• Est. Priority Date: 11/20/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Peleg, Nitzan
• Granted Patent: US 8,954,680 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A method, apparatus and product for data prefetching. The method comprising: prefetching data associated with a load instruction of a computer program, wherein the prefetching is performed in anticipation to performing the load instruction, whereby the data is retained in the cache; detecting whether the prefetched data of the prefetching is invalidated after the prefetching commenced and prior to performing the load instruction; and adaptively determining whether to modify the prefetching data operation associated with the load instruction in response to the detection.

Claims

1. A computer-implemented method performed by a processor having a cache, the method comprising:

prefetching data associated with a load instruction of a computer program, wherein said prefetching is performed in anticipation to performing the load instruction, whereby the data is retained in the cache;

detecting whether the prefetched data of said prefetching is invalidated after said prefetching commenced and prior to performing the load instruction; and

adaptively determining whether to modify the prefetching data operation associated with the load instruction in response to said detection.

2. The computer-implemented method of claim 1, wherein said adaptively determining comprises:

determining whether to avoid activating the prefetching data operation associated with the load instruction.

3. The computer-implemented method of claim 2, wherein said adaptively determining comprises:

calculating a ratio between a number of successful prefetching operations and unsuccessful prefetching operations, and determining to avoid prefetching data associated with the load instruction in response to the ratio being below a threshold.

4. The computer-implemented method of claim 2, wherein said adaptively determining comprises:

calculating a ratio between a cumulative estimated performance speedup of successful prefetching operations and cumulative estimated performance reductions of unsuccessful prefetching operations, and determining to avoid prefetching data associated with the load instruction in response to the ratio being below a threshold.

5. The computer-implemented method of claim 1, wherein said detecting comprises:

prior to commencing said prefetching, initiating a conflict detection transaction to detect a read-write conflict with data loaded by said prefetching, wherein the conflict detection transaction is configured to end upon completion of said prefetching; and

detecting a read-write conflict with data loaded during the conflict detection transaction.

6. The computer-implemented method of claim 1, wherein said detecting comprises utilizing a conflict detection module associated with hardware memory transaction module of the processor to detect the read/write conflict, wherein said prefetching is performed within a memory transaction, and whereby modification of the data, either by a same processing entity performing said prefethcing or a different processing entity, causes a conflict with the memory transaction.

7. The computer-implemented method of claim 1, wherein said prefetching is performed by a processing entity and wherein the load instruction is performed by a different processing entity.

8. The computer-implemented method of claim 1, wherein the load instruction is a delinquent load instruction of the computer program.

9. The computer-implemented method of claim 1, wherein the load instruction is an instruction within a critical section within the computer program.

10. The computer-implemented method of claim 1, wherein determining by said adaptively determining is stored and reused in future executions of the computer program by said processor or processors having similar configurations thereof.

11. The computer-implemented method of claim 1, wherein said adaptively determining comprises reducing expected time difference between said prefetching and performing of the load instruction.

12. The computer-implemented method of claim 1, wherein said prefetching is performed in anticipation to performing the load instruction comprises performing the prefetching at a determined timing prior to an expected timing of performing the load instruction, wherein the determined timing is about an expected cache miss latency associated with fetching the data.

13. A computerized apparatus comprising:

a memory, which is arranged to hold a computer program having a load instruction, wherein said memory is operatively coupled to a cache; and

a processor, having an associated cache, which is arranged to;

prefetch data associated with a load instruction of a computer program, wherein the prefetching is performed in anticipation to performing the load instruction, whereby the data is retained in the cache;

detect whether the prefetched data is invalidated after the prefetching commenced and prior to performing the load instruction; and

adaptively determine whether to modify the prefetching data operation associated with the load instruction in response to the detection.

14. The computerized apparatus of claim 13, wherein the adaptive determination is a determination whether to avoid activating the prefetching data operation associated with the load instruction.

15. The computerized apparatus of claim 14, wherein the adaptive determination comprises:

calculating a ratio between a number of successful prefetching operations and unsuccessful prefetching operations, and determining to avoid prefetching data associated with the load instruction in response to the ratio being below a threshold.

16. The computerized apparatus of claim 13, wherein the detection comprises:

prior to commencing the prefetching operation, initiating a conflict detection transaction to detect a read-write conflict with data loaded by the prefetching operation, wherein the conflict detection transaction is configured to end upon completion of the prefetching operation; and

detecting a read-write conflict with data loaded during the conflict detection transaction.

17. The computerized apparatus of claim 13, further comprising a hardware memory transaction module operatively coupled to said memory;

and wherein said processor is operative to detect prefetch invalidation by utilizing said hardware memory transaction module to detect a read-write conflict.

18. The computerized apparatus of claim 13, wherein said processor is operative to store the adaptive determination and reuse the adaptive determination in future executions of the computer program.

19. A computer program product comprising:

a non-transitory computer readable medium;

a first program instruction for prefetching data associated with a load instruction of a computer program, wherein said prefetching is performed in anticipation to performing the load instruction, whereby the data is retained in the cache;

a second program instruction for detecting whether the prefetched data of said prefetching is invalidated after said prefetching commenced and prior to performing the load instruction;

a third program instruction for adaptively determining whether to modify the prefetching data operation associated with the load instruction in response to said detection; and

wherein said first, second, and third program instructions are stored on said non-transitory computer readable medium.