PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

• US 20130132683A1
• Filed: 12/13/2012
• Published: 05/23/2013
• Est. Priority Date: 11/02/2006
• Status: Abandoned Application

• Current Assignee: Ajay V. Bhatt, Anil Vasudevan, Avi Mendelson, David J. Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark B. Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert G. Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Original Assignee: Ajay V. Bhatt, Anil Vasudevan, Avi Mendelson, David J. Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark B. Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert G. Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David J., Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Application Number:
  US13/713,614
• Publication Number:
  US 20130132683A1
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an I/O element to;

receive a packet of a transaction from a device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect;

identify, from the packet, a cache coherency attribute relating to cache coherency management associated with the transaction; and

cause the transaction to be completed based at least in part on the cache coherency attribute.

2. The apparatus of claim 1, wherein the transaction includes a request on shared memory.

3. The apparatus of claim 2, wherein the shared memory is a cache.

4. The apparatus of claim 3, wherein the shared memory is a system cache.

5. The apparatus of claim 3, wherein the shared memory is a local cache of a device.

6. The apparatus of claim 1, wherein cache coherency management includes snoop requests of one or more shared memory locations.

7. The apparatus of claim 6, wherein cache coherency management further includes filtering of the snoop request.

8. The apparatus of claim 7, wherein the one or more shared memory locations includes a first and second shared memory location, the transaction includes a request on the first shared memory location, and the cache coherency attribute is to indicate that snoop requests corresponding to the request should be filtered.

9. The apparatus of claim 8, wherein snoop requests of the second shared memory location are not filtered.

10. The apparatus of claim 8, wherein the cache coherency attribute is included in an attribute field of a transaction layer header of the packet.

11. The apparatus of claim 1, wherein the I/O element is included in a root controller of the apparatus.

12. The apparatus of claim 1, wherein the transaction includes an atomic operation.

13. An apparatus comprising:

a root controller including an I/O module configured to;

receive a packet of a transaction from a device over a point-to-point PCIe-compliant interconnect, wherein the I/O module includes a protocol stack including a transaction layer, a link layer, and a physical layer, the packet is a transaction layer packet including a transaction descriptor, the transaction descriptor includes a no-snoop field, and the transaction involves a request on shared memory;

identify, from the no-snoop field, whether snoop filtering applies to snoop requests of shared memory affected by the transaction; and

cause cache coherency management to be enforced associated with the transaction and based at least in part on the no-snoop field.

14. A method comprising:

receiving a packet of a transaction from a device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect;

identifying, from the packet, a cache coherency attribute relating to cache coherency management corresponding to the transaction; and

causing the transaction to be completed based at least in part on the cache coherency attribute.

15. The method of claim 14, wherein the cache coherency attribute indicates whether snoop filtering applies to the transaction.

16. The method of claim 15, further comprising filtering snoop requests based at least in part on the cache coherency attribute.

17. The method of claim 14, wherein the packet is included in a request on cache in the transaction.

18. A method comprising:

setting a value of a cache coherency attribute relating to cache coherency management associated with a transaction;

causing the cache coherency attribute to be included in a packet of the transaction; and

sending the packet to a device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect.

19. The method of claim 18, wherein the cache coherency attribute is included in a transaction layer header of the packet.

20. The method of claim 19, wherein the cache coherency attribute includes a no-snoop field.

21. The method of claim 20, wherein the no-snoop field indicates whether snoop requests are to be filtered in association with the transaction.

22. A system:

a first device;

a second device, including an I/O module executed by at least one processor to;

receive a packet of a transaction from the first device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect;

identify, from the packet, a cache coherency attribute relating to cache coherency management in association with the transaction; and

cause the transaction to be completed based at least in part on the cache coherency attribute.

23. The system of claim 22, wherein the first device is communicatively coupled to the second device using the interconnect.

24. The system of claim 22, wherein the first device comprises a root controller hub.

25. The system of claim 22, wherein the second device comprises a cache and the packet is included in a request of the cache by the first device.

26. The system of claim 22, wherein the second device Is further operable to:

set a cache coherency attribute value relating to cache coherency management in association with another transaction;

cause the cache coherency attribute value to be included in a packet of the other transaction; and

send the packet of the other transaction to another device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect.