RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION

• US 20130132913A1
• Filed: 11/23/2011
• Published: 05/23/2013
• Est. Priority Date: 11/23/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: FU, Chung-Min, HSU, Chin-Chang, LU, Yung-Fong, YANG, Wen-Ju
• Granted Patent: US 8,726,200 B2
• Time in Patent Office: Days
• US Class Current: 716/51
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Claims

1. Apparatus comprising:

a non-transitory machine readable storage medium for storing a template library having at least one template, the template to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an integrated circuit (IC), the pattern having a plurality of portions to be formed using a plurality of respectively different photomasks, the first layout representation including data identifying on which photomask each portion is to be located; and

an electronic design automation (EDA) tool comprising a computer configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons, the EDA tool having a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

2. The apparatus of claim 1, wherein:

the template library has a plurality of templates, each including a respective first layout representation of a respective pattern, each pattern having one or more portions to be formed using the plurality of photomasks;

the matching module identifies a matching set containing each of the plurality of templates that at least includes patterns matching all of the plurality of polygons in the part of the circuit, regardless of whether the patterns within one of the templates in the matching set are divided among two or more photomasks.

3. The apparatus of claim 2, wherein:

the matching module includes in the matching set each of the plurality of templates that at least includes patterns matching all of the plurality of polygons in the part of the circuit, regardless of whether any of the individual patterns includes two or more polygons that are closer to each other than a minimum separator distance for forming polygons with a single photomask.

4. The apparatus of claim 2, wherein:

the matching module includes in the matching set each of the plurality of templates that includes patterns that at least match all of the plurality of polygons in the part of the circuit, regardless of whether any of the individual templates includes a pattern matching, all of the plurality of polygons in the part of the circuit within a single photomask.

5. The apparatus of claim 2, wherein:

the matching module is configured to cause displaying of each template in the matching set.

6. The apparatus of claim 5, wherein;

the EDA tool is configured to respond to a selection by a user of one of the displayed templates by replacing the plurality of polygons in the part of the circuit with the selected template.

7. The apparatus of claim 5, wherein:

the matching module is configured to cause displaying of each polygon in the part of the circuit, wherein

the matching module is configured to cause the templates and polygons to be displayed in a manner that identifies on which photomask each portion of each pattern and each polygon of the part of the circuit is to be located.

8. The apparatus of claim 1, wherein:

the second layout representation includes data identifying on which photomask each of the plurality of polygons is to be located.

9. The apparatus of claim 8, wherein:

the matching module includes in the matching set each of the plurality of templates that includes a pattern matching at least one of the plurality of polygons in the part of the circuit.

10. The apparatus of claim 8, wherein:

the matching module includes in the matching set each of the plurality of templates that includes a pattern matching at least one of the plurality of polygons in the art of the circuit, regardless of whether any of the individual templates includes patterns matching all of the plurality of polygons to be formed within the photomask containing the at least one polygon.

11. The apparatus of claim 8, wherein:

the matching module includes in the matching set each of the plurality of templates that at least includes a pattern matching at least one of the plurality of polygons in the part of the circuit, so long as the template does not include within a single photomask a pattern corresponding to two polygons that are to be located in two different photomasks according to the data of the second layout representation identifying on which photomask each of the plurality of polygons is to be located.

12. A method comprising:

providing a non-transitory machine readable storage medium that stores a template library containing at least one template including a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC, the pattern having a plurality of portions to be formed using a plurality of respectively different photomasks, the first layout representation including data identifying on which photomask each portion is to be located;

using an electronic design automation (EDA) tool comprising a computer to generate a second layout representation of a part of a circuit having a plurality of polygons; and

identifying and outputting an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

13. The method of claim 12, wherein:

the template library has a plurality of templates, each including a respective first layout representation of a respective pattern, each pattern having one or more portions to be formed using the plurality of photomasks, the method further comprising;

identifying a matching set containing each of the plurality of templates that at least includes patterns matching all of the plurality of polygons in the part of the circuit, regardless of whether the patterns within one of the templates in the matching set are divided among two or more photomasks.

14. The method of claim 13, wherein:

the matching set includes each of the plurality of templates that includes patterns that at least match all of the plurality of polygons in the part of the circuit, regardless of whether any of the individual templates includes a pattern matching all of the plurality of polygons in the part of the circuit within a single photomask.

15. The method of claim 14, wherein outputting the indication includes displaying each template in the matching set;

and the method further comprises;

receiving a selection by a user of one of the displayed templates; and

responding to the selection by replacing the plurality of polygons in the part of the circuit with the selected template.

16. The method of claim 15, wherein:

the outputting further comprises displaying each polygon in the part of the circuit, and

the templates and polygons are each displayed in a manner that identifies on which photomask each portion of each pattern and each polygon of the part of the circuit is to be located.

17. The method of claim 12, wherein:

the second layout representation includes data identifying on which photomask each of the plurality of polygons is to be located; and

the matching set includes each of the plurality of templates that at least includes a pattern matching at least one of the plurality of polygons in the part of the circuit, so long as the template does not include within a single photomask a pattern corresponding to two polygons that are to be located in two different photomasks according to the data of the second layout representation identifying on which photomask each of the plurality of polygons is to be located.

18. A non-transitory machine readable storage medium encoded with computer program code, such that, when the computer program code is executed by a processor, the processor performs a method comprising:

accessing a non-transitory machine, readable storage medium that stores a template library containing at least one template including a first layout representation of at least one pattern to be formed by multi patterning a single layer of an IC, the pattern having a plurality of portions to be formed using a plurality of respectively different photomasks, the first layout representation including data identifying on which photomask each portion is to be located; and

using an electronic design automation (EDA) tool comprising a computer to generate a second layout representation of a part of a circuit having a plurality of polygons,

identifying and outputting an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

19. The non-transitory machine readable storage medium of claim 18, wherein:

the template library has a plurality of templates, each including a respective first layout representation of a respective pattern, each pattern having one or more portions to be formed using the plurality of photomasks, the method further comprising;

identifying a matching set containing each of the plurality of templates that at least includes patterns matching all of the plurality of polygons in the part of the circuit, regardless of whether the patterns within one of the templates in the matching set are divided among two or more photomasks, and regardless of whether any of the individual templates includes a pattern matching all of the plurality of polygons in the part of the circuit within a single photomask.

20. The non-transitory machine readable storage medium of claim 18, wherein:

outputting the indication includes displaying each template in the matching set and displaying each polygon in the part of the circuit, and

the templates and polygons are each displayed in a manner that identifies on which photomask each portion of each pattern and each polygon of the part of the circuit is to be located; and

the method further comprises;

receiving a selection by a user of one of the displayed templates; and

responding to the selection by replacing the plurality of polygons in the part of the circuit with the selected template.