THIN FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT EMITTING DISPLAY DEVICE COMPRISING THE SAME, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR ARRAY SUBSTRATE

• US 20130134424A1
• Filed: 06/28/2012
• Published: 05/30/2013
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, Dae-Woo, PARK, Jong-Hyun
• Granted Patent: US 9,153,605 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A thin film transistor array substrate may include a thin film transistor including an active layer, a gate electrode, source and drain electrodes, a first insulation layer arranged between the active layer and the gate electrode, and a second insulation layer arranged between the gate electrode and the source and drain electrodes, a pixel electrode arranged on the first insulation layer and comprising the same material as the gate electrode, a capacitor comprising a first electrode arranged on the same layer as the active layer and a second electrode arranged on the same layer as the gate electrode, a pad electrode arranged on the second insulation layer and comprising the same material as the source and drain electrodes, a protection layer formed on the pad electrode, and a third insulation layer formed on the protection layer and exposing the pixel electrode.

Claims

1. A thin film transistor array substrate, comprising:

a thin film transistor comprising an active layer, a gate electrode, source and drain electrodes, a first insulation layer arranged between the active layer and the gate electrode, and a second insulation layer arranged between the gate electrode and the source and drain electrodes;

a pixel electrode arranged on the first insulation layer and comprising the same material as the gate electrode;

a capacitor comprising a first electrode arranged on the same layer as the active layer and a second electrode arranged on the same layer as the gate electrode;

a pad electrode arranged on the second insulation layer and comprising the same material as the source and drain electrodes;

a protection layer formed on the pad electrode; and

a third insulation layer formed on the protection layer and exposing the pixel electrode.

2. The thin film transistor array substrate of claim 1, wherein the active layer comprises a semiconductor material doped with ion impurities.

3. The thin film transistor array substrate of claim 1, wherein the pixel electrode comprises transparent conductive oxide.

4. The thin film transistor array substrate of claim 3, wherein the transparent conductive oxide comprises at least one selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium galium oxide (IGO), and aluminum zinc oxide (AZO).

5. The thin film transistor array substrate of claim 1, wherein the first electrode comprises a semiconductor material doped with ion impurities.

6. The thin film transistor array substrate of claim 1, wherein a gap is formed between an end portion of the pixel electrode and an end portion of the second insulation layer.

7. The thin film transistor array substrate of claim 1, wherein an end portion of the pixel electrode and an end portion of the third insulation layer are overlapped each other.

8. The thin film transistor array substrate of claim 1, wherein a gap is formed between an end portion of the second electrode and an end portion of the second insulation layer.

9. The thin film transistor array substrate of claim 8, wherein the third insulation layer directly contacts the first insulation layer in the gap.

10. The thin film transistor array substrate of claim 1, wherein the protection layer is further formed on the source electrode and the drain electrode.

11. The thin film transistor array substrate of claim 1, wherein the pad electrode comprises a plurality of metal layers having different electron mobility.

12. The thin film transistor array substrate of claim 11, wherein the plurality of metal layers comprise a layer including molybdenum (Mo) and a layer including aluminum (Al).

13. The thin film transistor array substrate of claim 1, wherein the protection layer comprises metal oxide or transparent conductive oxide.

14. The thin film transistor array substrate of claim 13, wherein the transparent conductive oxide comprises at least one selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium galium oxide (IGO), and aluminum zinc oxide (AZO).

15. The thin film transistor array substrate of claim 1, wherein a gap is formed between an end portion of the pad electrode and an end portion of the protection layer.

16. The thin film transistor array substrate of claim 15, wherein the third insulation layer directly contacts an upper surface of the pad electrode in the gap.

17. The thin film transistor array substrate of claim 1, wherein the gate electrode comprises a first layer including transparent conductive oxide and a second layer including metal.

18. The thin film transistor array substrate of claim 1, wherein the gate electrode and the source and drain electrodes comprise the same material.

19. An organic light emitting display device, comprising:

a thin film transistor comprising an active layer, a gate electrode, source and drain electrodes, a first insulation layer arranged between the active layer and the gate electrode, and a second insulation layer arranged between the gate electrode and the source and drain electrodes;

a pixel electrode arranged on the first insulation layer and comprising the same material as the gate electrode;

a capacitor comprising a first electrode arranged on the same layer as the active layer and a second electrode arranged on the same layer as the gate electrode;

a pad electrode arranged on the second insulation layer and comprising the same material as the source and drain electrodes;

a protection layer formed on the pad electrode;

a third insulation layer formed on the protection layer and exposing the pixel electrode;

an organic light emitting layer arranged on the pixel electrode; and

an opposed electrode arranged on the organic light emitting layer.

20. The organic light emitting display device of claim 19, wherein the opposed electrode is a reflection electrode for reflecting light irradiated from the organic light emitting layer.

21. A method of manufacturing a thin film transistor array substrate, the method comprising:

a first mask process of forming a semiconductor layer on a substrate and forming an active layer of a thin film transistor and a first electrode of a capacitor by patterning the semiconductor layer;

a second mask process of forming a first insulation layer, forming a transparent conductive oxide layer and a first metal layer on the first insulation layer, and forming a pixel electrode, a gate electrode of the thin film transistor, and a second electrode of the capacitor by patterning the transparent conducive oxide layer and the first metal layer;

a third mask process of forming a second insulation layer and forming openings in the second insulation layer to allow the second insulation layer to expose the pixel electrode, source and drain areas of the active layer, and the first electrode;

a fourth mask process of forming a second metal layer and a protection layer on a resultant of the third mask process, forming a source electrode and a drain electrode respectively connected to the source area and the drain area, and a pad electrode, by patterning the second metal layer and the protection layer, and removing the first metal layer of the pixel electrode and the first metal layer of the second electrode; and

a fifth mask process of forming a third insulation layer and forming openings in the third insulation layer to expose the pixel electrode.

22. The method of claim 21, wherein, after the second mask process, ion impurities are doped into the source and drain areas.

23. The method of claim 21, wherein, in the third mask process, an opening of the second insulation layer is formed to form a gap between an end portion of the pixel electrode and an end portion of the second insulation layer.

24. The method of claim 21, wherein, in the third mask process, an opening of the second insulation layer is formed to form a gap between an end portion of the first electrode and an end portion of the second insulation layer.

25. The method of claim 21, wherein the first metal layer and the second metal layer are formed of the same material.

26. The method of claim 21, wherein the second metal layer comprises a plurality of metal layers having different electron mobility.

27. The method of claim 21, wherein the protection layer is formed of metal oxide or transparent conductive oxide.

28. The method of claim 21, wherein the fourth mask process comprises:

a first etch process for etching the first metal layer, the second metal layer, and the protection layer; and

a second etch process for etching the protection layer.

29. The method of claim 28, wherein an etchant to which oxalic acid or anti-metal corrosion agent is added is used in the second etch process.

30. The method of claim 21, wherein, after the fourth mask process, ion impurities are doped into the first electrode.