Semiconductor Device and Manufacturing Method thereof

• US 20130134488A1
• Filed: 07/18/2012
• Published: 05/30/2013
• Est. Priority Date: 11/24/2011
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Fumitake, Mieno
• Granted Patent: US 8,518,781 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Claims

1. A fin semiconductor device, comprising:

a fin including a semiconductor layer formed on a substrate;

an insulating material layer formed over the substrate and surrounding the fin, the insulating material layer having a thickness less than the thickness of the semiconductor layer;

a source region portion and a drain region portion formed on the insulating material layer; and

a first channel control region, a second channel control region and a channel region between the source region portion and the drain region portion,

wherein the first channel control region is at a center of the semiconductor layer away from the edge and has a first conductivity type,

wherein the second channel control region is formed along an edge of the semiconductor layer in a portion of the semiconductor layer that is not covered by the insulating material layer, the second channel control region having the first conductivity type,

wherein the channel region is between the first channel control region and the second channel control region, adjoining the source region portion and the drain region portion, wherein the channel region, the source region portion and the drain region portion have a second conductivity type which is opposite to the first conductivity type.

2. The semiconductor device of claim 1 further comprising:

a gate for the fin, the gate adjoining the second channel control region, wherein the gate is formed on the insulating material layer.

3. The semiconductor device of claim 1, wherein the first channel control region has a lower portion and an upper portion extending from the lower portion, wherein the lower portion is below the upper surface of the insulating material layer.

4. The semiconductor device of claim 1, wherein the fin further comprises a hard mask on the semiconductor layer.

5. The semiconductor device of claim 1, wherein a ratio of the thickness T of the insulating material layer to the difference between the height Hsemi of the semiconductor layer and the thickness T, that is, T/(Hsemi−

T), is about 3-5.

6. The semiconductor device of claim 1, wherein the second channel control region extends below the upper surface of the insulating material layer.

7. The semiconductor device of claim 1, wherein the substrate further has a region adjoining the first channel control region and having a conductivity type opposite to that of the channel region, so as to provide power for the first channel control region.

8. The semiconductor device of claim 1 further comprises:

gate spacers located on two sides of the gate that are adjacent to the source region portion and the drain region portion.

9. The semiconductor device of claim 1, further comprising two or more of the fins, wherein the two or more of the fins comprise a first fin and a second fin, and wherein the conductivity type of the channel region included in the first fin is the same as or opposite to the conductivity type of the channel region included in the second fin.

10. A method of manufacturing a semiconductor device, comprising:

providing a substrate with a fin formed thereon, wherein the fin has a semiconductor layer formed of a semiconductor material having a first conductivity type;

forming, over the substrate, a first insulating material layer surrounding the fin, wherein the first insulating material layer has a thickness less than the thickness of the semiconductor layer;

introducing, into an exposed surface of the semiconductor layer, a first dopant that can impart a second conductivity type which is opposite to the first conductivity type, such that a first region having the second conductivity type is formed at least in the exposed surface of the semiconductor layer in a portion of the fin that is not covered by the first insulating material layer, wherein, the portion of the semiconductor layer other than the first region serves as a second region, the second region having the first conductivity type;

forming a dummy gate for the fin to enclose a portion of the fin that corresponds to a channel region to be formed, wherein the dummy gate is formed above the first insulating material layer;

forming a second insulating material layer on the substrate to cover a portion of the fin other than the top surface of the dummy gate;

removing the dummy gate to expose a portion of the first region in the fin that is enclosed by the dummy gate; and

forming a third region having the first conductivity type in the first region by introducing into the first region a second dopant that can impart the first conductivity type,

wherein, the portion of the first region other than the third region is the channel region, the channel region separating the second region from the third region and having the second conductivity type, and

wherein, the second region is used for providing a first channel control region for controlling the channel region, and the third region functions as a second channel control region for controlling the channel region.

11. The method of claim 10, further comprising forming a hard mask on the semiconductor layer.

12. The method of claim 10 further comprising:

after forming the dummy gate but before forming the second insulating material layer, forming a spacer for the dummy gate,

wherein, the formed second insulating material layer also substantially covers the spacer.

13. The method of claim 12 further comprising:

after forming the spacer but before forming the second insulating material layer, implanting to form a source region portion and a drain region portion in the semiconductor layer that adjoin the channel region, the source region portion and the drain region portion has a conductivity type as same as that of the channel region,

wherein, the first channel control region in the second region is adjacent to said source region portion and the drain region portion and is between the source region and the drain region.

14. The method of claim 10 further comprising:

after introducing the second dopant, forming a gate for the fin, the gate adjoins the second channel control region from an outer side of the second channel control region, wherein the gate is formed above the first insulating material layer.

18. The method of claim 10, wherein a ratio of the thickness, T, of the insulating material layer to the difference between the height, Hsemi, of the semiconductor layer and the thickness T, that is, T/(Hsemi−

T), is 3-5.

19. The method of claim 10, wherein the substrate has two or more of the fins formed thereon, wherein the two or more of the fins comprise a first fin and a second fin, and wherein the conductivity type of the channel region in the first fin is same as or opposite to the conductivity type of the channel region in the second fin.

20. The method of claim 19, wherein the conductivity type of the channel region of the first fin is opposite to the conductivity type of the channel region of the second fin, further comprising:

introducing the first/second dopant by;

covering the first fin with a first mask and exposing the second fin, introducing a corresponding dopant into the second fin;

removing the first mask; and

covering the second fin with a second mask and exposing the first fin, and introducing a corresponding dopant into the first fin.

15. The method of claim 30 further comprising

after forming the gate, forming a spacer for the gate.

16. The method of claim 15 further comprising:

after forming the spacer, epitaxially growing a semiconductor material from the exposed surface of the semiconductor layer.

17. The method of claim 15 further comprising:

implanting to form a source region portion and a drain region portion in the semiconductor layer that adjoin the channel region, the source region portion and the drain region portion having a conductivity type that is the same as that of the channel region, and

wherein, the first channel control region in the second region is adjacent to the source region portion and the drain region portion and is between the source region portion and the drain region portion.