SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER

• US 20130134507A1
• Filed: 11/21/2012
• Published: 05/30/2013
• Est. Priority Date: 11/24/2011
• Status: Abandoned Application

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: TAKAISHI, Yoshihiro
• Application Number:
  US13/683,191
• Publication Number:
  US 20130134507A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.

Claims

1. A semiconductor device comprising:

a high-breakdown voltage transistor including at least first and second vertical transistors which are connected in series,

wherein the first vertical transistor comprises a first unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,

wherein the second vertical transistor comprises a second unit transistor group comprising a plurality of unit transistors each of which includes a semiconductor pillar,

wherein the plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared.

2. The semiconductor device as claimed in claim 1, wherein the first and the second vertical transistors are disposed in an active region.

3. The semiconductor device as claimed in claim 2,

wherein the plurality of unit transistors constituting the first unit transistor group comprise first pillar upper diffusion layers which are connected in parallel to each other,

wherein the plurality of unit transistors constituting the second unit transistor group comprise second pillar upper diffusion layers which are connected in parallel to each other.

4. The semiconductor device as claimed in claim 3,

wherein the plurality of unit transistors constituting the first unit transistor group comprise:

a first semiconductor pillar group comprising a plurality of semiconductor pillars;

the pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

the first pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the plurality of unit transistors constituting the second unit transistor group comprise;

a second semiconductor pillar group comprising a plurality of semiconductor pillars;

the pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

the second pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group.

5. The semiconductor device as claimed in claim 2,

wherein the first unit transistor group comprises:

a first semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in a predetermined direction with a space therebetween;

first gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

first gate electrodes which are formed over side faces of the plurality of semiconductor pillars constituting the first semiconductor pillar group via the first gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the second unit transistor group comprises;

a second semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in the predetermined direction with a space therebetween;

second gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

second gate electrode which are formed over side faces of the plurality of semiconductor pillars constituting the second semiconductor pillar group via the second gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the second semiconductor pillar group.

6. The semiconductor device as claimed in claim 5, wherein the first gate electrodes and the second gate electrodes are electrically connected to each other.

7. The semiconductor device as claimed in claim 5, wherein the first gate electrodes and the second gate electrodes are electrically separated from each other.

8. The semiconductor device as claimed in claim 3, wherein the first and the second vertical transistors constitute a serial/parallel transistor, a plurality of serial/parallel transistors being disposed so as to connect in series.

9. The semiconductor device as claimed in claim 1, wherein the first and the second vertical transistors are disposed in first and second active regions, respectively, which are adjacent to each other in a state where an element separation area is sandwiched therebetween,

wherein the plurality of unit transistors constituting the first unit transistor group have first pillar lower diffusion layers which are shared,

wherein the plurality of unit transistors constituting the second unit transistor group have second pillar lower diffusion layers which are shared.

10. The semiconductor device as claimed in claim 9,

wherein the plurality of unit transistors constituting the first unit transistor group comprise first pillar upper diffusion layers which are connected in parallel to each other,

wherein the plurality of unit transistors constituting the second unit transistor group comprise second pillar upper diffusion layers which are connected in parallel to each other.

11. The semiconductor device as claimed in claim 9,

wherein the plurality of unit transistors constituting the first unit transistor group comprise:

a first semiconductor pillar group comprising a plurality of semiconductor pillars;

the pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

the first pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the plurality of unit transistors constituting the second unit transistor group comprise;

a second semiconductor pillar group comprising a plurality of semiconductor pillars;

the pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

the second pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group.

12. The semiconductor device as claimed in claim 9, wherein the first pillar lower diffusion layers are connected in series to the second pillar lower diffusion layers.

13. The semiconductor device as claimed in claim 9,

wherein the first unit transistor group comprises:

a first semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in a predetermined direction with a space therebetween;

first gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

first gate electrodes which are formed over side faces of the plurality of semiconductor pillars constituting the first semiconductor pillar group via the first gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the second unit transistor group comprises;

a second semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in the predetermined direction with a space therebetween;

second gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

second gate electrode which are formed over side faces of the plurality of semiconductor pillars constituting the second semiconductor pillar group via the second gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the second semiconductor pillar group.

14. The semiconductor device as claimed in claim 9,

wherein the first vertical transistor further comprises a third unit transistor group which is disposed adjacent to the first unit transistor group and which comprises a plurality of unit transistors each including a semiconductor pillar, the plurality of unit transistors constituting the first and the third unit transistor groups having first and third pillar lower diffusion layers, respectively, each of which are shared,

wherein the second vertical transistor further comprises a fourth unit transistor group which is disposed adjacent to the second unit transistor group and which comprises a plurality of unit transistors each including a semiconductor pillar, the plurality of unit transistors constituting the second and the fourth unit transistor groups having second and fourth pillar lower diffusion layers, respectively, each of which are shared.

15. The semiconductor device as claimed in claim 14,

wherein the plurality of unit transistors constituting the first unit transistor group comprise first pillar upper diffusion layers which are connected in parallel to each other,

wherein the plurality of unit transistors constituting the second unit transistor group comprise second pillar upper diffusion layers which are connected in parallel to each other,

wherein the plurality of unit transistors constituting the third unit transistor group comprise third pillar upper diffusion layers which are connected in parallel to each other,

wherein the plurality of unit transistors constituting the fourth unit transistor group comprise fourth pillar upper diffusion layers which are connected in parallel to each other.

16. The semiconductor device as claimed in claim 15,

wherein the plurality of unit transistors constituting the first unit transistor group comprise:

a first semiconductor pillar group comprising a plurality of semiconductor pillars;

the first pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

the first pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the plurality of unit transistors constituting the second unit transistor group comprise;

a second semiconductor pillar group comprising a plurality of semiconductor pillars;

the second pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

the second pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the second semiconductor pillar group,

wherein the plurality of unit transistors constituting the third unit transistor group comprise;

a third semiconductor pillar group comprising a plurality of semiconductor pillars;

the third pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the third semiconductor pillar group; and

the third pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the plurality of unit transistors constituting the fourth unit transistor group comprise;

a fourth semiconductor pillar group comprising a plurality of semiconductor pillars;

the fourth pillar lower diffusion layer disposed in lower end portions of the plurality of semiconductor pillars constituting the fourth semiconductor pillar group; and

the fourth pillar upper diffusion layers disposed in respective upper end portions of the plurality of semiconductor pillars constituting the fourth semiconductor pillar group.

17. The semiconductor device as claimed in claim 15, wherein the first pillar upper diffusion layers are connected in series to the fourth pillar upper diffusion layers.

18. The semiconductor device as claimed in claim 14,

wherein the first unit transistor group comprises:

a first semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in a predetermined direction with a space therebetween;

first gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the first semiconductor pillar group; and

first gate electrodes which are formed over side faces of the plurality of semiconductor pillars constituting the first semiconductor pillar group via the first gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the first semiconductor pillar group,

wherein the second unit transistor group comprises;

a second semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in the predetermined direction with a space therebetween;

second gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the second semiconductor pillar group; and

second gate electrode which are formed over side faces of the plurality of semiconductor pillars constituting the second semiconductor pillar group via the second gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the second semiconductor pillar group,

wherein the third unit transistor group comprises;

a third semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in the predetermined direction with a space therebetween;

third gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the third semiconductor pillar group; and

third gate electrodes which are formed over side faces of the plurality of semiconductor pillars constituting the third semiconductor pillar group via the third gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the third semiconductor pillar group,

wherein the fourth unit transistor group comprises;

a fourth semiconductor pillar group comprising a plurality of semiconductor pillars which are formed in the predetermined direction with a space therebetween;

fourth gate insulating films which are provided on respective outer circumferential surfaces of the plurality of semiconductor pillars constituting the fourth semiconductor pillar group; and

fourth gate electrode which are formed over side faces of the plurality of semiconductor pillars constituting the fourth semiconductor pillar group via the fourth gate insulating films so as to fill gaps between the plurality of semiconductor pillars constituting the fourth semiconductor pillar group.

19. The semiconductor device as claimed in claim 18,

wherein the first gate electrodes and the third gate electrodes are commonly connected to each other so as to fill gaps between the plurality of semiconductor pillars constituting the first and the third semiconductor pillar groups,

wherein the second gate electrodes and the fourth gate electrodes are commonly connected to each other so as to fill gaps between the plurality of semiconductor pillars constituting the second and the fourth semiconductor pillar groups.

20. The semiconductor device as claimed in claim 18, wherein the first gate electrodes, the second gate electrodes, the third gate electrodes, and the fourth gate electrodes are electrically connected to each other.