INLINE IMAGE ROTATION

• US 20130135351A1
• Filed: 11/29/2011
• Published: 05/30/2013
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh, Bhargava, Nitin, Okruhlica, Craig M.
• Granted Patent: US 8,797,359 B2
• Time in Patent Office: Days
• US Class Current: 345/649
• CPC Class Codes: G06T 3/606 by memory addressing or mapping
• CPC Class Codes: G09G 2340/0492 Change of orientation of the displayed image, e.g. upside-down, mirrored
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Methods and apparatus for performing an inline rotation of an image. The apparatus includes a rotation unit for reading pixels from a source image in an order based on a specified rotation to be performed. The source image is partitioned into multiple tiles, the tiles are processed based on where they will be located within the rotated image, and each tile is stored in a tile buffer. The target pixel addresses within a tile buffer are calculated and stored in a lookup table, and when the pixels are retrieved from the source image by the rotation unit, the lookup table is read to determine where to write the pixels within a corresponding tile buffer.

Claims

1. An apparatus comprising:

a fetch unit; and

a memory coupled to the fetch unit;

wherein the fetch unit is configured to generate a plurality of read operations to read pixels from a source image stored in the memory, wherein the plurality of read operations are generated in an order that is based on a rotation being performed on the source image.

2. The apparatus as recited in claim 1, further comprising one or more tile buffers, wherein the fetch unit is further configured to write the pixels to specific locations of a given tile buffer, wherein the specific locations are determined based on the rotation being performed on the source image.

3. The apparatus as recited in claim 2, wherein the source image comprises a plurality of tiles, and wherein each tile buffer is configured to store a single tile of the source image.

4. The apparatus as recited in claim 3, wherein a width of each tile is less than a width of the source image, and wherein a length of each tile is less than a length of the source image.

5. The apparatus as recited in claim 4, wherein each tile buffer comprises an individual random access memory (RAM) for each row of the tile.

6. The apparatus as recited in claim 1, wherein the plurality of read operations are direct memory access (DMA) operations.

7. The apparatus as recited in claim 3, further comprising a table configured to store target pixel locations, wherein the target pixel locations correspond to locations in a given tile buffer, and wherein the fetch unit is configured to:

write the target pixel locations into the table responsive to generating a corresponding read operation;

responsive to receiving pixels from a given read operation, retrieving target pixel locations from the table; and

writing the received pixels to the target pixel locations within a given tile buffer.

8. The apparatus as recited in claim 7, wherein the table is configured to store a transaction identifier (ID) for each entry in the table, wherein the transaction ID corresponds to a specific read operation, and wherein responsive to receiving pixels from the specific read operation, the fetch unit is configured to utilize a corresponding entry in the table to determine target pixel locations within a given tile buffer.

9. The apparatus as recited in claim 7, wherein the fetch unit is configured to generate a given read operation while simultaneously writing corresponding target pixel locations into the table.

10. The apparatus as recited in claim 1, further comprising a memory management unit (MMU), wherein the fetch unit is configured to generate virtual addresses for the plurality of read operations, and wherein the MMU is configured to:

translate the virtual addresses to physical addresses within the memory;

perform read operations to the physical addresses; and

convey retrieved pixels to the fetch unit.

11. The apparatus as recited in claim 10, wherein the fetch unit is further configured to generate prefetch requests to preload virtual address translations.

12. A rotation unit configured to:

receive configuration bits indicating a selected rotation to be performed on a source image;

issue read requests for the source image, wherein the read requests are issued in an order based on the selected rotation;

for each read request, calculate target positions of corresponding pixels in a rotated image, wherein the rotated image is the source image after the selected rotation has been performed;

store the calculated target positions in a table;

receive the pixels from the source image; and

retrieve the calculated target positions and store the received pixels at the calculated target positions within a tile buffer.

13. The rotation unit as recited in claim 12, wherein the source image is partitioned into a plurality of tiles, wherein the tiles are read from the source image in an order based on the selected rotation, and wherein the tile buffer is utilized to store an individual tile of the rotated image.

14. The rotation unit as recited in claim 13, wherein responsive to a subsequent stage of a graphics pipeline fetching the pixels from the tile buffer, the rotation unit is configured to issue read requests for a subsequent tile of the source image.

15. The rotation unit as recited in claim 12, wherein the source image is an individual frame of a video stream.

16. A method comprising:

issuing fetch requests for pixels from a source image, wherein an order in which the fetch requests are issued is based on a specified rotation;

calculating target locations for the pixels, wherein the target locations are calculated based on the specified rotation, and wherein the target locations correspond to locations within a rotated version of the source image; and

receiving and storing the pixels in a tile buffer at the calculated target locations.

17. The method as recited in claim 16, further comprising:

storing the calculated target locations in a table responsive to issuing the fetch requests; and

looking up the calculated target locations in the table responsive to receiving the pixels.

18. The method as recited in claim 17, wherein each pixel comprises a plurality of color components, and wherein each color component of the plurality of color components is stored in a separate tile buffer.

19. The method as recited in claim 16, wherein the source image is partitioned into a plurality of tiles, and wherein fetch requests are issued for pixels from a given tile starting at a top row of the given tile and moving down the given tile row-by-row.

20. A method comprising:

partitioning a source image into a plurality of tiles, wherein the partitioning is based on a specified rotation;

reading pixels from a first tile of the source image;

storing the pixels from the first tile in target locations within a tile buffer, wherein the target locations are calculated based on the specified rotation;

responsive to detecting the tile buffer has been read by a subsequent stage in a graphics pipeline;

reading pixels from a second tile of the source image; and

storing the pixels from the second tile in the tile buffer.

21. The method as recited in claim 20, wherein an order of the first and second tiles within the source image is based on the specified rotation.

22. The method as recited in claim 20, wherein the subsequent stage of the graphics pipeline is a scaler unit.

23. The method as recited in claim 22, wherein the tile buffer comprises a plurality of individual random access memories (RAMs), and wherein the scaler unit is configured to read a single pixel from each RAM in a single clock cycle.