MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER

• US 20130135916A1
• Filed: 11/26/2012
• Published: 05/30/2013
• Est. Priority Date: 11/28/2011
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: OSANAI, Fumiyuki, SUGANO, Toshio, HIRAISHI, Atsushi
• Granted Patent: US 9,076,500 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Claims

1. A memory module comprising:

a module substrate having first and second main surfaces opposite to each other, the first main surface having first and second memory mounting areas, one of the first and second main surfaces having a register mounting area located between the first and second memory mounting areas in a planner view;

a plurality of data connectors formed on the module substrate;

a plurality of memory devices including a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area; and

a plurality of data register buffers mounted on the register mounting area, the data register buffers transferring write data supplied from the data connectors to the memory devices, and transferring read data supplied from the memory devices to the data connectors.

2. The memory module as claimed in claim 1, wherein

the first memory devices are arranged in a first direction in the first memory mounting area,

the second memory devices are arranged in the first direction in the second memory mounting area,

the data register buffers are arranged in the first direction in the register mounting area, and

each of the data register buffers and associated ones of the first and second memory devices connected thereto are arranged in a second direction crossing the first direction in the planner view.

3. The memory module as claimed in claim 1, wherein the first memory devices and the second memory devices are activated in common.

4. The memory module as claimed in claim 1, wherein the first memory devices and the second memory devices are mounted in 180°

different directions.

5. The memory module as claimed in claim 1, wherein

the second main surface of the module substrate has third and fourth memory mounting areas,

the plurality of memory devices further include a plurality of third memory devices that are mounted on the third memory mounting area and a plurality of fourth memory devices that are mounted on the fourth memory mounting area,

the first memory devices and the third memory devices are mounted in overlapping positions in the planner view,

the second memory devices and the fourth memory devices are mounted in overlapping positions in the planner view, and

each of data register buffers and associated ones of the third and fourth memory devices connected thereto are arranged in a second direction crossing the first direction in the planner view.

6. The memory module as claimed in claim 5, wherein

the third memory devices and the fourth memory devices are activated in common, and

the first and second memory devices and the third and fourth memory devices are exclusively activated.

7. The memory module as claimed in claim 5, wherein

the first memory devices and the second memory devices are mounted in 180°

different directions; and

the third memory devices and the fourth memory devices are mounted in 180°

different directions.

8. The memory module as claimed in claim 5, wherein

the first main surface of the module substrate further has fifth and sixth memory mounting areas,

the second main surface of the module substrate further has seventh and eighth memory mounting areas,

the plurality of memory devices further include a plurality of fifth memory devices that are mounted on the fifth memory mounting area, a plurality of sixth memory devices that are mounted on the sixth memory mounting area, a plurality of seventh memory devices that are mounted on the seventh memory mounting area, and a plurality of eighth memory devices that are mounted on the eighth memory mounting area,

the register mounting area is arranged between the fifth and sixth memory mounting areas in the planner view,

the fifth memory devices and the seventh memory devices are mounted in overlapping positions in the planner view,

the sixth memory devices and the eighth memory devices are mounted in overlapping positions in the planner view, and

each of the data register buffers and associated ones of the fifth to eighth memory devices connected thereto are arranged in the second direction in the planner view.

9. The memory module as claimed in claim 8, wherein

the fifth memory devices and the sixth memory devices are activated in common,

the seventh memory devices and the eighth memory devices are activated in common,

the first and second devices, the third and fourth memory devices, the fifth and sixth memory devices, and the seventh and eighth memory devices are exclusively activated.

10. The memory module as claimed in claim 8, wherein

the fifth memory mounting area is arranged between the first memory mounting area and the register mounting area in the planner view, and

the second memory mounting area is arranged between the sixth memory mounting area and the register mounting area in the planner view.

11. The memory module as claimed in claim 8, wherein

the first memory devices and the fifth memory devices are mounted in 180°

different directions,

the second memory devices and the sixth memory devices are mounted in 180°

different directions,

the third memory devices and the seventh memory devices are mounted in 180°

different directions, and

the fourth memory devices and the eighth memory devices are mounted in 180°

different directions.

12. The memory module as claimed in claim 8, further comprising first and second command address register buffers that are mounted on the module substrate, wherein

the first command address register buffer supplies a command address signal to the first to fourth memory devices, and

the second command address register buffer supplies a command address signal to the fifth to eighth memory devices.

13. The memory module as claimed in claim 1, wherein each of the memory devices includes one or more memory chips.

14. A memory module comprising:

a module substrate;

a data connector formed at one side of the memory module;

a data register buffer mounted on the memory module and electrically connected to the data connector;

first and second memory devices electrically connected in common to the data register buffer, the first and second memory devices being mounted on the memory module such that the data register buffer are arranged between the first and second memory devices.

15. The memory module as claimed in claim 14, wherein

the first memory device includes a first data terminal electrically connected to the data register buffer,

the second memory device includes a second data terminal electrically connected to the data register buffer,

a dimensional relationship between a center position and the first data terminal of the first memory device is 180°

different from a dimensional relationship between a center position and the second data terminal of the second memory device.

16. The memory module as claimed in claim 14, further comprising third and fourth memory devices electrically connected in common to the data register buffer,

wherein the data register buffer and first to fourth memory devices are arranged in line.