LDPC Erasure Decoding for Flash Memories

• US 20130139035A1
• Filed: 03/11/2011
• Published: 05/30/2013
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Zhong, Hao, Li, Yan, Danilak, Radoslav, Cohen, Earl T.
• Granted Patent: US 8,935,595 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: H03M 13/373 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing

Abstract

A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

Claims

1. A system comprising:

a means for requesting, in response to receiving a request for data stored at a particular location in a flash memory, one or more initial reads at the particular location;

a means for detecting, in response to completing the initial reads, an uncorrectable error via a hard-decision based Low Density Parity Check (LDPC) decoding based on results of the initial reads;

a means for requesting, in response to the means for detecting, one or more additional reads at the particular location; and

a means for performing, in response to completing the additional reads, an erasure-decision LDPC decoding based on respective results of the additional reads.

2. The system of claim 1 wherein the flash memory comprises Single-Level Cell (SLC) technology flash memory, the initial reads are one in number, the additional reads are two in number, and each of the additional reads is at a respective read voltage.

3. The system of claim 2 further comprising a means for providing respective voltage specifiers for each of the additional reads.

4. The system of claim 3 wherein at least one of the voltage specifiers is one of an explicit voltage level, an identifier of one of a plurality of predetermined voltage levels, and a unique identification of one of a plurality of read request types.

5. The system of claim 1 wherein the flash memory comprises Multi-Level Cell (MLC) technology flash memory.

6. The system of claim 1 wherein the receiving is compatible with one or more of a plurality of interface standards, the interface standards comprising

a Serial Advanced Technology Attachment (SATA) interface standard,

a Serial Attached Small Computer System Interface (SAS) interface standard,

a Peripheral Component Interconnect express (PCIe) interface standard,

a Fibre Channel interface standard, and

an Ethernet interface standard.

7. The system of claim 1 wherein the means for requesting initial reads and the means for requesting additional reads are via a controller, the controller and the flash memory are comprised in a storage sub-system implemented as one of a plurality of non-volatile storage component types, and the non-volatile storage component types comprise

a Universal Serial Bus (USB) storage component type,

a Compact Flash (CF) storage component type,

a MultiMediaCard (MMC) storage component type,

a Secure Digital (SD) storage component type,

a Memory Stick storage component type, and

an xD-picture card storage component type.

8. A method comprising:

requesting, in response to receiving a request for data stored at a particular location in a flash memory, one or more initial reads at the particular location;

detecting, in response to completing the initial reads, an uncorrectable error via a hard-decision based Low Density Parity Check (LDPC) decoding based on results of the initial reads;

requesting, in response to the detecting, one or more additional reads at the particular location; and

performing, in response to completing the additional reads, an erasure-decision LDPC decoding based on respective results of the additional reads.

9. The method of claim 8 wherein the flash memory comprises Single-Level Cell (SLC) technology flash memory, the initial reads are one in number, the additional reads are two in number, and each of the additional reads is at a respective read voltage.

10. The method of claim 9 further comprising providing respective voltage specifiers for each of the additional reads.

11. The method of claim 10 wherein at least one of the voltage specifiers is one of an explicit voltage level, an identifier of one of a plurality of predetermined voltage levels, and a unique identification of one of a plurality of read request types.

12. The method of claim 8 wherein the flash memory comprises Multi-Level Cell (MLC) technology flash memory.

13. The method of claim 8 wherein the receiving is compatible with one or more of a plurality of interface standards, the interface standards comprising

a Serial Advanced Technology Attachment (SATA) interface standard,

a Serial Attached Small Computer System Interface (SAS) interface standard,

a Peripheral Component Interconnect express (PCIe) interface standard,

a Fibre Channel interface standard, and

an Ethernet interface standard.

14. The method of claim 8 wherein the requesting initial reads and the requesting additional reads are via a controller, the controller and the flash memory are comprised in a storage sub-system implemented as one of a plurality of non-volatile storage component types, and the non-volatile storage component types comprise

a Universal Serial Bus (USB) storage component type,

a Compact Flash (CF) storage component type,

a MultiMediaCard (MMC) storage component type,

a Secure Digital (SD) storage component type,

a Memory Stick storage component type, and

an xD-picture card storage component type.

15. A system comprising:

an interface; and

a controller enabled to

request, in response to receiving a request via the interface for data stored at a particular location in a flash memory, one or more initial reads at the particular location;

detect, in response to completing the initial reads, an uncorrectable error via a hard-decision based Low Density Parity Check (LDPC) decoding based on results of the initial reads;

request, in response to the detection, one or more additional reads at the particular location; and

perform, in response to completing the additional reads, an erasure-decision LDPC decoding based on respective results of the additional reads.

16. The system of claim 15 wherein the flash memory comprises Single-Level Cell (SLC) technology flash memory, the initial reads are one in number, the additional reads are two in number, and each of the additional reads is at a respective read voltage.

17. The system of claim 16 wherein the controller is further enabled to provide respective voltage specifiers for each of the additional reads.

18. The system of claim 17 wherein at least one of the voltage specifiers is one of an explicit voltage level, an identifier of one of a plurality of predetermined voltage levels, and a unique identification of one of a plurality of read request types.

19. The system of claim 15 wherein the flash memory comprises Multi-Level Cell (MLC) technology flash memory.

20. The system of claim 15 wherein the controller and the flash memory are comprised in a storage sub-system implemented as one of a plurality of non-volatile storage component types, and the non-volatile storage component types comprise

a Universal Serial Bus (USB) storage component type,

a Compact Flash (CF) storage component type,

a MultiMediaCard (MMC) storage component type,

a Secure Digital (SD) storage component type,

a Memory Stick storage component type, and

an xD-picture card storage component type.