Plating Process and Structure

• US 20130140563A1
• Filed: 12/02/2011
• Published: 06/06/2013
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kao, Chin-Fu, Huang, Cheng-Lin, Lin, Jing-Cheng
• Granted Patent: US 8,536,573 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/11825 Plating, e.g. electroplating, electroless plating
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13583 : Three-layer coating
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN

Abstract

A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.

Claims

1. A semiconductor device comprising:

a contact on a substrate, the contact comprising a first material with a first reduction potential, the first reduction potential being at a first end of a range of reduction potentials;

a test pad on the substrate, the test pad comprising a second material with a second reduction potential different from the first reduction potential, the second reduction potential being at a second end of the range of reduction potentials; and

at least one via electrically connecting the test pad to the contact, the at least one via comprising a third material with a third reduction potential, the third reduction potential being outside of the range of reduction potentials.

2. The semiconductor device of claim 1, wherein the third reduction potential is greater than the second reduction potential.

3. The semiconductor device of claim 1, wherein the third reduction potential is lower than the first reduction potential.

4. The semiconductor device of claim 1, wherein the first material comprises copper and the second material comprises aluminum.

5. The semiconductor device of claim 4, wherein the third material comprises magnesium.

6. The semiconductor device of claim 4, wherein the third material comprises platinum.

7. The semiconductor device of claim 1, further comprising a redistribution line electrically connecting the test pad to the at least one via.

8. A semiconductor device comprising:

a first metallization layer on a substrate, the first metallization layer comprising a test pad redistribution line and a first conductive connector separated from the test pad redistribution line, the test pad redistribution line and the first conductive connector comprising a first material with a first reduction potential;

a second metallization layer on the substrate, the second metallization layer comprising a conductive line and a second conductive connector separated from the conductive line, the conductive line electrically connected to a contact, the conductive line and the second conductive connector comprising a second material with a second reduction potential different from the first reduction potential;

a first via connecting the test pad redistribution line and the second conductive connector;

a second via connecting the second conductive connector to the first conductive connector; and

a third via connecting the first conductive connector to the conductive line.

9. The semiconductor device of claim 8, wherein the first via comprises the first material.

10. The semiconductor device of claim 8, wherein the first via comprises the second material.

11. The semiconductor device of claim 8, wherein the first material is aluminum and the second material is copper.

12. The semiconductor device of claim 8, wherein the first via comprises a third material with a third reduction potential different from the first reduction potential and the second reduction potential.

13. The semiconductor device of claim 12, wherein the third material is magnesium, the first material is aluminum, and the second material is copper.

14. The semiconductor device of claim 8, further comprising a conductive layer over the contact.

15. A semiconductor device comprising:

a test pad on a substrate, the test pad comprising a first material with a first reduction potential;

a contact pad on the substrate, the contact pad electrically connected to the test pad;

a contact stack over the contact pad, the contact stack comprising;

a contact, the contact comprising a second material with a second reduction potential different from the first reduction potential; and

a blocking layer comprising a third material with a third reduction potential different from the second reduction potential.

16. The semiconductor device of claim 15, wherein the blocking layer is located over the contact.

17. The semiconductor device of claim 15, wherein the blocking layer is located between the contact and the contact pad.

18. The semiconductor device of claim 17, further comprising a barrier layer located between the blocking layer and the contact pad.

19. The semiconductor device of claim 17, further comprising a barrier layer located between the blocking layer and the contact.

20. The semiconductor device of claim 15, wherein the test pad comprises aluminum, the contact comprises copper, and the blocking layer comprises nickel.