SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20130140582A1
• Filed: 04/15/2011
• Published: 06/06/2013
• Est. Priority Date: 10/15/2010
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kawakami, Tsuyoshi, Furukawa, Akihiko, Miura, Naruhisa, Kagawa, Yasuhiro, Hamada, Kenji, Nakaki, Yoshiyuki
• Granted Patent: US 8,716,717 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11′) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple. The fourth RESURF layer (14) is configured with small regions (13′) having an implantation amount equal to that of the third RESURF layer (13) and small regions (15′) having an implantation amount equal to that of the fifth RESURF layer (15) being alternately arranged in multiple.

Claims

1. A semiconductor device comprising:

an active region (2) formed in a surface of a semiconductor layer (1) having a first conductive type; and

a plurality of electric field relief layers that are defined by impurity regions having a second conductive type, said plurality of electric field relief layers being arranged from a peripheral portion of said active region toward the outside so as to surround said active region,

wherein

said plurality of electric field relief layers are configured such that an impurity implantation amount decreases from said active region side toward the outside,

said plurality of electric field relief layers include;

a first electric field relief layer whose entire region is implanted with an impurity having the second conductive type at a first surface density;

a second electric field relief layer whose entire region is implanted with an impurity having the second conductive type at a second surface density; and

a third electric field relief layer configured with a plurality of first small regions and a plurality of second small regions being alternately arranged, said first small region having a width in a plane direction smaller than that of said first electric field relief layer, said first small region being implanted with an impurity having the second conductive type at said first surface density, said second small region having a width in the plane direction smaller than that of said second electric field relief layer, said second small region being implanted with an impurity having the second conductive type at said second surface density,

said third electric field relief layer is arranged between said first electric field relief layer and said second electric field relief layer with respect to the plane direction, and the average surface density of said third electric field relief layer takes a value between said first surface density and said second surface density.

2. The semiconductor device according to claim 1, wherein

in said plurality of electric field relief layers,

a final electric field relief layer provided in the last when said active region is defined as the head is configured with a plurality of third small regions and a plurality of non-implanted regions being alternately arranged, said third small region having a width in the plane direction smaller than that of a pre-final electric field relief layer that immediately precedes said final electric field relief layer, said third small region being implanted with an impurity having the second conductive type at a surface density equal to that of said pre-final electric field relief layer, said non-implanted region being formed of said semiconductor layer not implanted with an impurity having the second conductive type.

3. The semiconductor device according to claim 1, wherein

in said second electric field relief layer,

the depth of implantation in the impurity region thereof is greater than the depth of implantation in the impurity region of said first electric field relief layer.

4. The semiconductor device according to claim 3, wherein

an impurity region that is formed simultaneously with said impurity region of said second electric field relief layer so as to have a depth and an impurity concentration equal to those of said impurity region of said second electric field relief layer contains, with respect to a cross-sectional direction, an impurity region that is formed simultaneously with said impurity region of said first electric field relief layer so as to have a depth and an impurity concentration equal to those of said impurity region of said first electric field relief layer.

5. The semiconductor device according to claim 1, wherein

in a case where said first electric field relief layer is provided adjacent to said active region, the depth of implantation and an implanted region of said impurity region are set such that said impurity region of said first electric field relief layer covers the peripheral portion of said active region or the whole of said active region.

6. The semiconductor device according to claim 5, wherein

said first electric field relief layer also serves as said active region.

7. The semiconductor device according to claim 1, wherein

said third electric field relief layer is formed such that one of said first and second small regions having a larger implantation amount have a constant width with respect to the plane direction, while the other of said first and second small regions having a smaller implantation amount have their width with respect to the plane direction gradually increasing at a location farther from said active region.

8. The semiconductor device according to claim 1, wherein

said third electric field relief layer formed such that one of said first and second small regions having a larger implantation amount have their width with respect to the plane direction gradually decreasing at a location farther from said active region, while the other of said first and second small regions having a smaller implantation amount have their width with respect to the plane direction gradually increasing at a location farther from said active region.

9. The semiconductor device according to claim 1, wherein

said active region corresponds to an anode region of a PN junction diode.

10. The semiconductor device according to claim 1, wherein

said active region corresponds to a region located below a Schottky electrode of a Schottky barrier diode.

11. The semiconductor device according to claim 1, wherein

said active region corresponds to a partial region of a transistor including a MOSFET, an IGBT, a BJT.

12. The semiconductor device according to claim 11, wherein

said active region corresponds to a drain region of an LDMOSFET (Laterally Diffused MOSFET) having a source electrode (95), a gate electrode (93), and a drain electrode (97) arranged in the plane direction on a main surface of said semiconductor layer,

said plurality of electric field relief layers are arranged between said drain region and a well region including a source region.

13. The semiconductor device according to claim 1, wherein

said semiconductor layer is made of a wide band-gap semiconductor.

14. A method for manufacturing the semiconductor device according to claim 1, said method comprising the steps of:

(a) forming a first implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said first surface density, to thereby form said first electric field relief layer and said first small regions; and

(b) after said step (a), forming a second implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said second surface density, to thereby form said second electric field relief layer and said second small regions.

15. A method for manufacturing the semiconductor device according to claim 1, said method comprising the steps of:

(a) forming a first implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said second surface density, so that an impurity layer that is identical to said second electric field relief layer is formed in a region where said first electric field relief layer is formed, and said second small regions are also formed; and

(b) after said step (a), forming, on said semiconductor layer, a second implantation mask that covers at least said second electric field relief layer, and ion-implanting the impurity having the second conductive type at a surface density that, when added to said second surface density, results in said first surface density, to thereby form said first electric field relief layer and said first small regions.