EDGE TERMINATION FOR SUPER JUNCTION MOSFET DEVICES

• US 20130140633A1
• Filed: 12/01/2011
• Published: 06/06/2013
• Est. Priority Date: 12/01/2011
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva N.
• Granted Patent: US 9,431,249 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.

Claims

1. A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:

a substrate;

a charge compensation region located above said substrate and comprising a plurality of columns of P type dopant within an N type dopant region;

a termination region located above said charge compensation region and comprising an N−

type dopant layer; and

an edge termination structure, wherein said termination region comprises a portion of said edge termination structure.

2. The Super Junction MOSFET device of claim 1, wherein said edge termination structure comprises a set of field rings and field plates.

3. The Super Junction MOSFET device of claim 1, wherein said edge termination structure comprises a set of field plates.

4. The Super Junction MOSFET device of claim 1, wherein said edge termination structure comprises a junction termination extension region.

5. The Super Junction MOSFET device of claim 1, further comprising:

a field effect transistor, said termination region comprising a portion of said field effect transistor.

6. The Super Junction MOSFET device of claim 5, wherein said field effect transistor comprises a P type dopant region that merges with one of said plurality of columns of P type dopant.

7. The Super Junction MOSFET device of claim 5, wherein said field effect transistor comprises a junction field effect transistor.

8. A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:

a substrate;

a charge compensation region located above said substrate and comprising a plurality of columns of N type dopant within a P type dopant region;

a termination region located above said charge compensation region and comprising a P−

type dopant layer; and

an edge termination structure, wherein said termination region comprises a portion of said edge termination structure.

9. The Super Junction MOSFET device of claim 8, wherein said edge termination structure comprises a set of field rings and field plates.

10. The Super Junction MOSFET device of claim 8, wherein said edge termination structure comprises a set of field plates.

11. The Super Junction MOSFET device of claim 8, wherein said edge termination structure comprises a junction termination extension.

12. The Super Junction MOSFET device of claim 8, further comprising:

a field effect transistor, said termination region comprising a portion of said field effect transistor.

13. The Super Junction MOSFET device of claim 12, wherein said field effect transistor comprises an N type dopant region that merges with one of said plurality of columns of N type dopant.

14. The Super Junction MOSFET device of claim 12, wherein said field effect transistor comprises a junction field effect transistor.

15. A method comprising:

generating a charge compensation region of a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device, wherein said charge compensation region is located above a substrate and comprising a plurality of columns of first type dopant within a second type dopant region;

generating a termination region located above said charge compensation region and comprising a lower concentration of said second type dopant than said second type dopant layer; and

generating an edge termination structure such that said termination region comprises at least a portion of said edge termination structure.

16. The method of claim 15, wherein said first type dopant comprises a P type dopant and said second type dopant comprises an N type dopant.

17. The method of claim 15, wherein said first type dopant comprises an N type dopant and said second type dopant comprises a P type dopant.

18. The method of claim 15, wherein said edge termination structure is selected from the group consisting of a field ring, a field plate, and a junction termination extension.

19. The method of claim 15, further comprising:

generating a field effect transistor such that said termination region comprises at least a portion of said field effect transistor.

20. The method of claim 19, wherein said generating said field effect transistor further comprises generating said field effect transistor that comprises a region of said first type dopant that merges with one of said plurality of columns of first type dopant.