SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130140635A1
• Filed: 03/23/2012
• Published: 06/06/2013
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Yan, Jing-Yi, Hsu, Chih-Chieh, Yao, Hsiao-Chiang, Hung, Chu-Yin
• Granted Patent: US 9,165,947 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Claims

1. A semiconductor device, comprising:

a gate and a first electrode, located on a substrate;

a first insulating layer, covering the gate and the first electrode;

an active layer and an etching stop layer, disposed on the first insulating layer above the gate and the first electrode respectively;

a second insulating layer, covering the active layer and the etching stop layer, wherein the second insulating layer has a first opening, a second opening and a third opening, the first opening and the second opening expose the active layer, and the third opening exposes the etching stop layer;

a source and a drain, disposed on the second insulating layer and contacting with the active layer through the first opening and the second opening respectively; and

a second electrode, located on the second insulating layer and contacting with the etching stop layer through the third opening.

2. The semiconductor device as claimed in claim 1, wherein the first opening and the second opening further expose two sides of the active layer, and the source and the drain contact with the two exposed sides of the active layer.

3. The semiconductor device as claimed in claim 1, further comprising a protecting auxiliary layer, located on the active layer and the etching stop layer, wherein the first opening, the second opening and the third opening pass through the protecting auxiliary layer.

4. The semiconductor device as claimed in claim 1, further comprising:

a third insulating layer, covering the source, the drain and the second electrode; and

a top gate, disposed on the third insulating layer above the active layer.

5. The semiconductor device as claimed in claim 4, wherein the top gate is electrically connected to the gate.

6. The semiconductor device as claimed in claim 4, wherein the top gate is electrically connected to a conductive line, and the conductive line and the gate are in the same film layer.

7. The semiconductor device as claimed in claim 4, wherein the top gate is electrically connected to a conductive line, and the conductive line and the source and the drain are in the same film layer.

8. The semiconductor device as claimed in claim 4, further comprising a third electrode, disposed on the third insulating layer above the second electrode.

9. The semiconductor device as claimed in claim 8, wherein the third electrode is electrically connected to the first electrode.

10. The semiconductor device as claimed in claim 1, wherein a material of the active layer is the same to a material of the etching stop layer.

11. A method of manufacturing a semiconductor device, comprising:

forming a first conductive layer on a substrate, the first conductive layer comprising a gate and a first electrode;

forming a first insulating layer to cover the first conductive layer;

forming a semiconductor layer on the first insulating layer, the semiconductor layer comprising an active layer and an etching stop layer;

forming a second insulating layer on the semiconductor layer;

patterning the second insulating layer to form a first opening, a second opening and a third opening, the first opening and the second opening exposing the active layer, and the third opening exposing the etching stop layer; and

forming a second conductive layer on the second insulating layer, the second conductive layer comprising a source, a drain and a second electrode, the source and the drain contacting with the active layer through the first opening and the second opening, and the second electrode contacting with the etching stop layer through the third opening.

12. The method as claimed in claim 11, further comprising performing a plasma treatment after pattering the second insulating layer so as to decrease a resistance of the active layer exposed by the first opening and the second opening and decrease a resistance of the etching stop layer exposed by the third opening.

13. The method as claimed in claim 12, wherein the plasma treatment comprising an argon gas plasma treatment, an oxygen gas plasma treatment or a helium gas plasma treatment.

14. The method as claimed in claim 11, wherein the first opening and the second opening further expose two sides of the active layer, and the source and the drain contact with the two exposed sides of the active layer.

15. The method as claimed in claim 11, further comprising forming a protecting auxiliary layer on the active layer and the etching stop layer, wherein the first opening, the second opening and the third opening pass through the protecting auxiliary layer.

16. The method as claimed in claim 11, further comprising:

forming a third insulating layer on the second insulating layer to cover the source, the drain and the second electrode; and

forming a top gate on the third insulating layer above the active layer.

17. The method as claimed in claim 16, further comprising forming a contact opening in the third insulating layer, the second insulating layer and the first insulating layer, the top gate being electrically connected to the gate through the contact opening.

18. The method as claimed in claim 16, wherein the first conductive layer further comprises a conductive line, and the top gate is electrically connected to the conductive line.

19. The method as claimed in claim 16, wherein the second conductive layer further comprises a conductive line, and the top gate is electrically connected to the conductive line.

20. The method as claimed in claim 16, further comprising forming a third electrode on the third insulating layer above the second electrode.

21. The method as claimed in claim 20, wherein the third electrode is electrically connected to the first electrode.

22. The method as claimed in claim 11, wherein the semiconductor layer comprises a metal oxide semiconductor material, an amorphous silicon material, a polysilicon material or a micro-crystal silicon material.