PLL CIRCUIT, CALIBRATION METHOD AND WIRELESS COMMUNICATION TERMINAL

• US 20130141146A1
• Filed: 02/17/2012
• Published: 06/06/2013
• Est. Priority Date: 03/07/2011
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Shima, Takahiro
• Granted Patent: US 8,508,268 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider.

Claims

1. A PLL circuit comprising:

a voltage controlled oscillator configured to output a high frequency signal;

an injection locked frequency divider configured to frequency-divide the output high frequency signal;

a frequency divider configured to frequency-divide the frequency-divided signal into a frequency of a reference signal;

a phase frequency detector configured to compare the frequency-divided signal from the frequency divider with the reference signal and configured to output a phase difference and a frequency difference;

a charge pump configured to convert the output phase difference and the frequency difference into an electric current;

a loop filter configured to generate a control voltage for the voltage controlled oscillator in accordance with the thus-converted electric current and configured to apply the generated control voltage to the voltage controlled oscillator; and

a calibration circuit configured to control an oscillation band which determines an oscillation frequency of the voltage controlled oscillator and configured to control a control parameter for activating the injection locked frequency divider in a determined operating range, wherein

the calibration circuit is configured to adjust the oscillation band of the voltage controlled oscillator in accordance with a frequency-divided signal of the adjusted injection locked frequency divider after adjustment of the control parameter of the injection locked frequency divider.

2. The PLL circuit according to claim 1, wherein the calibration circuit further includes

a VCO controller configured to control operation of the voltage controlled oscillator, and

an ILFD controller configured to control operation of the injection locked frequency divider, wherein

the VCO controller is configured to deactivate the voltage controlled oscillator when the ILFD controller adjusts the control parameter of the injection locked frequency divider.

3. The PLL circuit according to claim 2, wherein the calibration circuit further includes

a clock counter configured to measure a frequency of a frequency-divided signal which has been frequency-divided in accordance with a control signal including the control parameter and a frequency of the reference signal, wherein

the ILFD controller is configured to set the control parameter for the injection locked frequency divider when a difference exists between the measured frequency of the frequency-divided signal and the measured frequency of the reference signal.

4. The PLL circuit according to claim 2, wherein the calibration circuit further includes

a clock counter configured to measure a frequency of the frequency-divided signal which has been frequency-divided in accordance with a control signal including the control parameter and a frequency of the reference signal, wherein

the ILFD controller is configured to set the control parameter for the injection locked frequency divider on the basis of the measured frequency of the frequency-divided signal and the measured frequency of the reference signal.

5. The PLL circuit according to claim 3, wherein the VCO controller is configured to release the voltage controlled oscillator from a deactivated state after setting the control parameter for the injection locked frequency divider and select the oscillation band for determining an oscillation frequency of the voltage controlled oscillator.

6. The PLL circuit according to claim 5, wherein the VCO controller is configured to select another oscillation band of the voltage controlled oscillator when a frequency of a signal, which is output from the voltage controlled oscillator in accordance with the selected oscillation band, differs from a frequency of the reference signal and a frequency of a frequency-divided signal which has been frequency-divided by the injection locked frequency divider and by the frequency divider.

7. The PLL circuit according to claim 5, wherein the VCO controller is configured to select the oscillation band of the voltage controlled oscillator on the basis of a frequency of a frequency-divided signal that is obtained by frequency-dividing a signal, which is output from the voltage controlled oscillator according to the selected oscillation band, by means of the injection locked frequency divider and the frequency divider, and a frequency of the reference signal.

8. The PLL circuit according to claim 6, further comprising a lookup table configured to store the oscillation band of the voltage controlled oscillator and the control parameter of the injection locked frequency divider when the frequency of the frequency-divided signal and the frequency of the reference signal comes close to each other.

10. A wireless communication terminal comprising:

the PLL circuit defined in claim 1;

a modulator configured to modulate a baseband transmission signal;

a transmission mixer configured to produce, by means of frequency conversion, a carrier frequency from a first local signal output from the PLL circuit and the modulated transmission signal; and

a receiving mixer configured to produce, by means of frequency conversion, a baseband signal from a second local signal output from the PLL circuit and a received signal; and

a demodulator configured to demodulate the frequency-converted received signal.

9. A calibration method comprising:

deactivating operation of a voltage controlled oscillator configured to output a high frequency signal;

measuring a frequency of a frequency-divided signal which is obtained by frequency-dividing in accordance with a control signal including a control parameter of an injection locked frequency divider for frequency-dividing the high frequency signal and a frequency of a determined reference signal;

setting the control parameter of the injection locked frequency divider in accordance with the measured frequency of the frequency-divided signal and the frequency of the reference signal;

releasing the voltage controlled oscillator from a deactivated state;

selecting an oscillation band that determines an oscillation frequency of the voltage controlled oscillator; and

selecting the oscillation band of the voltage controlled oscillator on the basis of a frequency of a frequency-divided signal that is obtained by frequency-dividing a signal, which is output from the voltage controlled oscillator according to the selected oscillation band, by means of the injection locked frequency divider and the frequency divider, and a frequency of the reference signal.