Orthogonally Referenced Integrated Ensemble for Navigation and Timing

• US 20130141172A1
• Filed: 01/18/2013
• Published: 06/06/2013
• Est. Priority Date: 04/08/2011
• Status: Active Grant

• Current Assignee: UT-Battelle LLC
• Original Assignee: UT-Battelle LLC
• Inventors: Smith, Stephen Fulton, Moore, James Anthony
• Granted Patent: US 8,686,804 B2
• Time in Patent Office: Days
• US Class Current: 331/15
• CPC Class Codes: G01C 21/10 by using measurements of speed or acceleration G01C21/24, G01C21/26 take precedence
• CPC Class Codes: G01P 15/097 by vibratory elements
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01S 1/045 Receivers
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03B 5/30 with frequency-determining element being electromechanical resonator
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/01 Details
• CPC Class Codes: H03L 1/028 of generators comprising piezoelectric resonators H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Claims

1. A dual-polyhedral oscillator array, comprising:

an outer sensing array of oscillators, comprising;

a first pair of sensing oscillators situated along a first axis of the outer sensing array,

a second pair of sensing oscillators situated along a second axis of the outer sensing array, and

a third pair of sensing oscillators situated along a third axis of the outer sensing array; and

an inner clock array of oscillators situated inside the outer sensing array, comprising;

a first pair of clock oscillators situated along a first axis of the inner clock array,

a second pair of clock oscillators situated along a second axis of the inner clock array, and

a third pair of clock oscillators situated along a third axis of the inner clock array.

2. The dual-polyhedral oscillator of claim 1, wherein:

each of the first pair of sensing oscillators is situated on opposite sides of the first axis of the outer sensing array;

each of the second pair of sensing oscillators is situated on opposite sides of the second axis of the outer sensing array;

each of the third pair of sensing oscillators is situated on opposite sides of the third axis of the outer sensing array;

each of the first pair of clock oscillators is situated on opposite sides of the first axis of the inner clock array;

each of the second pair of clock oscillators is situated on opposite sides of the second axis of the inner clock array; and

each of the third pair of clock oscillators is situated on opposite sides of the third axis of the inner clock array.

3. The dual-polyhedral oscillator array of claim 1, further comprising a master oscillator coupled to the first pair of clock oscillators, the second pair of clock oscillators and the third pair of clock oscillators.

4. The dual-polyhedral oscillator array of claim 1,

wherein the first pair of clock oscillators, the second pair of clock oscillators and the third pair of clock oscillators comprise low-gamma oscillators;

and

wherein the first pair of sensing oscillators, the second pair of sensing oscillators, and the third pair of sensing oscillators comprise high-gamma oscillators.

5. The dual-polyhedral oscillator array of claim 1, wherein the first pair of clock oscillators, the second pair of clock oscillators, the third pair of clock oscillators, the first pair of sensing oscillators, the second pair of sensing oscillators, and the third pair of sensing oscillators comprise dual-mode oscillators.

6. The dual-polyhedral oscillator array of claim 1, wherein the outer sensing array and the inner clock array each comprises a cubic array.

7. A differential oscillator, comprising:

a crystal operable to oscillate in a main mode and in a secondary mode, the crystal further operable to output an oscillation signal;

a first circuit operable to separate a main signal of the main mode from the oscillation signal; and

a second circuit operable to separate a secondary signal of the secondary mode from the oscillation signal;

wherein;

the first circuit and the second circuit are disposed in a substantially symmetrical differential layout, and

the first circuit and the second circuit each comprises an automated oscillator gain-control (AGC) loop coupled to the crystal.

8. The differential oscillator of claim 7, wherein the AGC loop comprises a feedback network operable to regulate oscillator loop gain.

9. The differential oscillator of claim 7, wherein the AGC loop comprises a balanced bridge network operable to regulate oscillator loop gain, wherein the balanced bridge network includes a single-ended gain-control device to regulate the oscillator loop gain while maintaining approximate balance in the balanced bridge network.

10. The differential oscillator of claim 7, wherein the single-ended gain-control device comprises a junction gate field-effect transistor (JFET).

11. The differential oscillator of claim 8, wherein the feedback network comprises a plurality of resistors coupled in series.

12. The differential oscillator of claim 8, wherein the feedback network comprises an isolation hybrid RF-style combiner.

13. The differential oscillator of claim 7, wherein the AGC loop comprises a transformer.

14. The differential oscillator of claim 7, wherein the first circuit and the second circuit each comprises a plurality of inductors operable to provide alternating current (AC) isolation.

15. The differential oscillator of claim 7, further comprising a bias string coupled to the second circuit, the bias string operable to provide temperature compensation of a bias current, the bias string comprising a plurality of diode-connected transistors.

16. A multi-mode oscillator, comprising:

a crystal operable to oscillate in a main mode, in a secondary mode and in a tertiary mode, the crystal further operable to output an oscillation signal;

a first circuit operable to separate a main signal of the main mode from the oscillation signal;

a second circuit operable to separate a secondary signal of the secondary mode from the oscillation signal;

a third circuit operable to separate a third signal of the tertiary mode from the oscillation signal; and

a signal processor coupled to the first circuit, the second circuit and the third circuit, the signal processor configured to;

generate a first output signal based on the main signal and the secondary signal in response to the secondary mode being stable, and

generate a second output signal based on the main signal and the tertiary signal in response to the secondary mode being unstable or unreliable.

17. The multi-mode oscillator of claim 16, wherein the main mode comprises a third-overtone C mode, the secondary mode comprises a third-overtone B mode, and the tertiary mode comprises a fundamental C mode.

18. The multi-mode oscillator of claim 16, wherein the main mode comprises a third-overtone C mode, the secondary mode comprises a third-overtone B mode, and the tertiary mode comprises a fifth-overtone B mode.

19. The multi-mode oscillator according to claim 16, wherein the crystal comprises a doubly-rotated stress-compensated cut crystal.

20. The dual-mode oscillator according to claim 16, wherein the crystal comprises a doubly rotated IT-cut crystal.

21. A method for reducing mode-jumping in a dual-mode oscillator, comprising:

driving a crystal operable to oscillate in two different modes in an oscillator loop; and

modifying a signal in the oscillator loop to reduce mode-jumping.

22. The method of claim 21, wherein modifying the signal in the oscillator loop comprises increasing an oscillator frequency at a controlled rate during oscillator startup.

23. The method of claim 21, wherein modifying the signal in the oscillator loop comprises summing at least a harmonic or a sub-harmonic with the signal.

24. The method of claim 21, further comprising:

monitoring an oscillator loop phase to determine whether a mode-jumping has occurred;

wherein modifying the signal in the oscillator loop comprises;

if the mode-jumping is determined to have occurred, modifying the oscillator loop phase by a phase shift component, a harmonics component, or a phase-controlled harmonic component to shift the crystal to a desired mode.

25. The method of claim 21, wherein modifying the signal in the oscillator loop comprises limiting a rate of phase change in the oscillator loop by at least one of an analog or a digital technique.

26. An electronic automatic oscillator gain-control (AGC) circuit comprising a balanced bridge network operable to regulate circuit gain, wherein the balanced bridge network comprises a single-ended gain-control device operable to regulate the circuit gain while maintaining approximate balance in the balanced bridge network.

27. The electronic AGC circuit of claim 26, wherein the single-ended gain-control device comprises a junction gate field-effect transistor (JFET).

28. The electronic AGC circuit of claim 26, further comprising an electronically adjustable differential attenuator, the electronically adjustable differential attenuator configured to exhibit noise contributions from only one device.

29. The electronic AGC circuit of claim 26, further comprising an electronically variable differential attenuator, the electronically variable differential attenuator including only linear circuit elements.

30. The electronic AGC circuit of claim 26, further comprising an electronically variable differential attenuator, the electronically variable differential attenuator configured to exhibit noise contributions from only one active device and fixed resistors.