ARRAY SUBSTRATE AND DISPLAY DEVICE

• US 20130141660A1
• Filed: 08/29/2012
• Published: 06/06/2013
• Est. Priority Date: 08/29/2011
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Bai, Feng, Wang, Benlian, Zhang, Zhiqin
• Granted Patent: US 9,324,764 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13456 Cell terminals located on one side of the display only
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: G02F 2201/506 Repairing, e.g. with redundant arrangement against defective part
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/156 two-dimensional arrays

Abstract

Embodiments of the present invention relate to an array substrate and a display device comprising the array substrate. According to an embodiment of the invention, there is provided an array substrate which comprises: a terminal region; and an active pixel region, the active pixel region comprising: a plurality of pixel units; a plurality of gate lines; a plurality of data lines; and a plurality of gate leading wires, wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires.

Claims

1. An array substrate, comprising:

a terminal region; and

an active pixel region, the active pixel region comprising;

a plurality of pixel units;

a plurality of gate lines;

a plurality of data lines; and

a plurality of gate leading wires,

wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires.

2. The array substrate claimed as claim 1, wherein the number of the plurality of gate lines is twice as many as the row number of the plurality of pixel units, and two of the gate lines are provided between two rows of pixel units among the plurality of pixel units.

3. The array substrate claimed as claim 1, wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there are provided a source driver and a gate driver, the plurality of data lines each are connected to the source driver, and the plurality of gate leading wires each are connected to the gate driver.

4. The array substrate claimed as claim 1, wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there is provided a source-gate integrated driver, the plurality of data lines and the plurality of gate leading wires each are connected to the source-gate integrated driver.

5. The array substrate claimed as claim 1, wherein the plurality of gate leading wires and the plurality of data lines are located in the same layer, the plurality of gate leading wires are parallel to the plurality of data lines, each of the plurality of gate leading wires is electrically connected to respective one of the plurality of gate lines through a via hole.

6. The array substrate claimed as claim 1, wherein one or two of the plurality of gate leading wires are provided between the two columns of the plurality of pixel units.

7. The array substrate claimed as claim 1, wherein the array substrate further comprises a dummy line, the dummy line is disposed between the two columns of the pixel units and is a leading wire not being connected to every gate line of the plurality of gate lines.

8. The array substrate claimed as claim 7, wherein the number of the dummy line disposed between the two columns of the pixel units is one or two.

9. The array substrate claimed as claim 8, wherein the number of the plurality of gate lines is 640, the number of the plurality of data lines is 360, the number of the plurality of gate leading wires is 640, and respective two of the gate leading wires are disposed between the two columns of the pixel units of each of any 320 groups, each group having two columns of the pixel units.

10. The array substrate claimed as claim 9, wherein respective two of the dummy lines are disposed between the two columns of the pixel units of each of remaining 40 groups.

11. The array substrate claimed as claim 1, wherein the plurality of gate leading wires and the plurality of data lines are located in the different layers.

12. A display device, comprising:

an array substrate, including;

a terminal region; and

an active pixel region, the active pixel region comprising;

a plurality of pixel units;

a plurality of gate lines;

a plurality of data lines; and

a plurality of gate leading wires;

a color filter substrate, disposed opposite the array substrate; and

a liquid crystal layer, interposed between the array substrate and the color filter substrate,

wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires.

13. The display device claimed as claim 12, wherein number of the plurality of gate lines is twice as many as the row number of the plurality of pixel units, and two of the gate lines are provided between two rows of pixel units among the plurality of pixel units.

14. The display device claimed as claim 12, wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there are provided a source driver and a gate driver, the plurality of data lines each are connected to the source driver, and the plurality of gate leading wires each are connected to the gate driver.

15. The display device claimed as claim 12, wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there is provided a source-gate integrated driver, the plurality of data lines and the plurality of gate leading wires each are connected to the source-gate integrated driver.

16. The display device claimed as claim 12, wherein the plurality of gate leading wires and the plurality of data lines are located in the same layer, the plurality of gate leading wires are parallel to the plurality of data lines, each of the plurality of gate leading wires is electrically connected to respective one of the plurality of gate lines through a via hole.

17. The display device claimed as claim 12, wherein the array substrate further comprises a dummy line, the dummy line is disposed between the two columns of the pixel units and is a leading wire not being connected to every gate line of the plurality of gate lines.

18. The display device claimed as claim 17, wherein the number of dummy line disposed between the two columns of the pixel units is one or two.

19. The display device claimed as claim 12, wherein the plurality of gate leading wires and the plurality of data lines are located in the different layers.

20. The display device claimed as claim 12, wherein one or two of the plurality of gate leading wires are provided between the two columns of the plurality of pixel units.