NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20130141971A1
• Filed: 09/22/2011
• Published: 06/06/2013
• Est. Priority Date: 09/24/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosono, Koji
• Granted Patent: US 9,230,665 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A control circuit provides an at least partially negative threshold voltage distribution to a memory cell, thereby erasing retained data of the memory cell, and provides multiple levels of positive threshold voltage distributions thereto, thereby programming multiple levels of data to the memory cell. The control circuit, when executing a program operation to the memory cell, executes a first program operation that provides the multiple levels of positive threshold voltage distributions to a first memory cell which is a memory cell subject to program, and executes a second program operation that provides a positive threshold voltage distribution, to a second memory cell adjacent to the first memory cell, irrespective of (regardless of) whether data to be programmed to the second memory cell is (already) present in the second memory cell or not.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells; and

a control circuit configured to control a voltage applied to the plurality of memory cells,

the control circuit being configured to, when executing a program operation, execute a first program operation so that a first memory cell selected by the control circuit retains data whose threshold voltage is a positive value, and execute a second program operation so that a second memory cell adjacent to the first memory cell is set to a positive threshold voltage.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cell array includes a plurality of memory strings, each of the memory strings further including a plurality of the memory cells connected in series,

each of the memory strings comprising:

a semiconductor layer functioning as a body of the memory cells;

a memory gate insulating film including a charge storage layer capable of storing a charge, and being formed continuously, including between the plurality of the memory cells; and

a conductive layer formed on the memory gate insulating film, and functioning as a gate of the memory cells.

3. The nonvolatile semiconductor memory device according to claim 1, wherein

the control circuit is configured to execute the second program operation to the second memory cell after the first program operation to the first memory cell.

4. The nonvolatile semiconductor memory device according to claim 2, wherein

the control circuit is configured to execute the second program operation to the second memory cell after the first program operation to the first memory cell.

5. The nonvolatile semiconductor memory device according to claim 3, wherein

each of the memory cells is capable of retaining 2-or-more-bits data, and

the control circuit is configured to, when the control circuit receives a certain part of the 2-or-more-bits data as a first data and a program execution command, start the first program operation for programming part of the first data to the first memory cell and then start the second program operation to the second memory cell, and,

when the control circuit receives complete 2-or-more-bits data and a program command after the first program operation for programming the part of the first data to the first memory cell and before the second program operation to the second memory cell start, execute the first program operation for programming complete 2-or-more-bits data as the first data prior to the second program operation to the second memory cell.

6. The nonvolatile semiconductor memory device according to claim 4, wherein

each of the memory cells is capable of retaining 2-or-more-bits data, and

the control circuit is configured to, when the control circuit receives a certain part of the 2-or-more-bits data as a first data and a program execution command, start the first program operation for programming part of the first data to the first memory cell and then start the second program operation to the second memory cell, and,

when the control circuit receives complete 2-or-more-bits data and a program command after the first program operation for programming the part of the first data to the first memory cell and before the second program operation to the second memory cell start, execute the first program operation for programming complete 2-or-more-bits data as the first data prior to the second program operation to the second memory cell.

7. The nonvolatile semiconductor memory device according to claim 1, wherein

the control circuit is configured to execute the second program operation to the second memory cell before the first program operation to the first memory cell.

8. The nonvolatile semiconductor memory device according to claim 2, wherein

the control circuit is configured to execute the second program operation to the second memory cell before the first program operation to the first memory cell.

9. The nonvolatile semiconductor memory device according to claim 1, further comprising a data retaining circuit configured to retain page data to be programmed to the memory cells,

wherein the control circuit is configured to abandon the page data retained in the data retaining circuit every time programming a certain amount of data is finished, and retain page data to be programmed next.

10. The nonvolatile semiconductor memory device according to claim 2, further comprising a data retaining circuit configured to retain page data to be programmed to the memory cells,

wherein the control circuit is configured to abandon the page data retained in the data retaining circuit every time programming a certain amount of data is finished, and retain page data to be programmed next.

11. The nonvolatile semiconductor memory device according to claim 1, wherein

each of the memory cells is capable of retaining 2-or-more-bits data, and

the control circuit is configured capable of executing an first program operation in a lump when the control circuit receives the 2-or-more-bits data to be programmed to the first memory cell before the first program operation is executed to the first memory cell.

12. The nonvolatile semiconductor memory device according to claim 2, wherein

each of the memory cells is capable of retaining 2-or-more-bits data, and

the control circuit is configured capable of executing an first program operation in a lump when the control circuit receives the 2-or-more-bits data to be programmed to the first memory cell before the first program operation is executed to the first memory cell.

13. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cell array includes a first region and a second region, and

when the control circuit executes an erase operation to the memory cells,

the control circuit controls so as to set memory cells in the second region and to the memory cells in the first region that are adjacent to the memory cells in the second region, to the positive threshold voltage, and to set memory cells in the first region excluding the memory cells in the first region that are adjacent to the memory cells in the second region, to a threshold voltage lower than the positive threshold voltage.

14. The nonvolatile semiconductor memory device according to claim 13, wherein

when the control circuit executes an erase operation on the memory cells,

the control circuit, performs the erase operation for providing a first threshold voltage distribution to the memory cells in the second region, and then executes the second program operation, and

the control circuit performs the erase operation for providing the first threshold voltage distribution to the memory cells in the first region, and then retains the memory cells unchanged in a state of having been applied with the first threshold voltage distribution.

15. The nonvolatile semiconductor memory device according to claim 13, wherein

the memory cell array comprises a plurality of memory blocks,

each of the memory blocks comprises:

a plurality of memory strings each including the memory cells connected in series;

a plurality of drain side select transistors each connected to each of first ends of the memory strings; and

a plurality of source side select transistors each connected to each of second ends of the memory strings, and

the nonvolatile semiconductor memory device comprises;

a plurality of word lines disposed so as to be commonly connected to a plurality of the memory strings disposed in one of the plurality of memory blocks;

a plurality of bit lines extending in a first direction and connected to one end of the drain side select transistor existing in the plurality of memory blocks;

a source line commonly connected to one end of the source side select transistor;

a drain side select gate line provided so as to commonly connect a gate of the drain side select transistor aligned in a second direction orthogonal to the first direction,; and

a source side select gate line provided so as to commonly connect a gate of the source side select transistor aligned in the second direction, and provided having the second direction as a longer direction.

16. The nonvolatile semiconductor memory device according to claim 15, wherein

each of the memory strings comprises:

a semiconductor layer functioning as a body of the memory cells;

a memory gate insulating film including a charge storage layer capable of storing a charge and formed continuously, including between the plurality of the memory cells, in a direction that the plurality of memory cells are aligned along the semiconductor layer; and

a word line conductive layer formed on the memory gate insulating film, and functioning as a gate of the memory cells and as the word lines.

17. The nonvolatile semiconductor memory device according to claim 15, further comprising:

a first dummy memory cell provided between the first end of the memory string and the drain side select transistor; and

a second dummy memory cell provided between the second end of the memory string and the source side select transistor,

wherein

the first dummy memory cell and the second dummy memory cell comprise a charge storage film for storing a charge, and are configured capable of retaining multiple levels of threshold voltage distributions according to an amount of charge stored, and

the control circuit is configured to not program data to the first dummy memory cell and the second dummy memory cell.

18. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a memory cell array including a plurality of memory blocks;

a plurality of sub-blocks provided in the memory block, and arranged along a first direction parallel to the substrate; and

a control circuit configured to control a voltage supplied to the sub-blocks,

each of the sub-blocks comprising;

a plurality of memory strings arranged in a row along a second direction parallel to the substrate, and each including a plurality of memory cells connected in series along a perpendicular direction with respect to the substrate;

a plurality of drain side select transistors each connected to each of first ends of the memory strings; and

a plurality of source side select transistors each connected to each of second ends of the memory strings,

the memory cells arranged in the first direction and the second direction having gates commonly connected to each other,

the drain side select transistors arranged in the second direction having gates commonly connected to each other,

the source side select transistors arranged in the second direction having gates commonly connected to each other,

each of the memory cells comprising a charge storage film for storing a charge, and being configured capable of retaining multiple levels of threshold voltage distributions according to an amount of charge stored,

wherein, an address bit to select a sub-block is allocated lower than an address bit to select a word line connecting to the gates commonly connected among the memory cells.

19. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a memory cell array including a plurality of memory blocks;

a plurality of sub-blocks provided in the memory block, and arranged along a first direction parallel to the substrate; and

a control circuit configured to control a voltage supplied to the sub-blocks,

each of the sub-blocks comprising;

a plurality of memory strings arranged in a row along a second direction parallel to the substrate, and each including a plurality of memory cells connected in series along a perpendicular direction with respect to the substrate;

a plurality of drain side select transistors each connected to each of first ends of the memory strings; and

a plurality of source side select transistors each connected to each of second ends of the memory strings,

the memory cells arranged in the first direction and the second direction having gates commonly connected to each other,

the drain side select transistors arranged in the second direction having gates commonly connected to each other,

the source side select transistors arranged in the second direction having gates commonly connected to each other,

each of the memory cells comprising a charge storage film for storing a charge, and being configured capable of retaining multiple levels of threshold voltage distributions according to an amount of charge stored,

wherein, an address bit to select a word line connecting to the gates commonly connected among the memory cells is allocated lower than an address bit to select a sub-block.