Receiving Circuit, Method for Receiving a Signal, and Use of a Detection Circuit and a Control Circuit

• US 20130143508A1
• Filed: 01/28/2013
• Published: 06/06/2013
• Est. Priority Date: 04/14/2008
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Beyer, Sascha, Ferchland, Tilo, Hanusch, Thomas
• Granted Patent: US 9,264,128 B2
• Time in Patent Office: Days
• US Class Current: 455/226.1
• CPC Class Codes: H04B 17/20 of receivers
• CPC Class Codes: H04B 7/204 Multiple access
• CPC Class Codes: H04L 1/1867 Arrangements specially adapted for the transmitter end

Abstract

A receiving circuit, method for receiving a signal, and use of a detection circuit and a control circuit of a receiving circuit of a node of a radio network is provided to deactivate an analog signal processing and/or determination of digital data from a signal received over an antenna of the node, when a stored current frame of the digital data has been recognized as valid, and to activate the analog signal processing and/or the determination, when the transmission of the current frame over an interface of the control circuit has been confirmed, whereby the control circuit is connected to the detection circuit and/or an input circuit for deactivation and activation, and whereby the detection circuit is formed to determine the digital data from the received signal.

Claims

1. A receiving circuit of a node of a radio network, the receiving circuit comprising:

an input circuit that is connectable to an antenna to receive a signal;

an evaluation circuit that is connected downstream of the input circuit in the receive path, and

wherein the input circuit is configured for analog signal processing with an analog-to-digital conversion of the received signal into a digital signal, and

wherein the evaluation circuit is configured to evaluate the digital signal and has a detection circuit, a check circuit, and a control circuit, the detection circuit being configured to determine digital data from the digital signal, the check circuit being configured to save the digital data and to check a current frame of the digital data and to output at least one test signal based on the checking, and the control circuit being connected to the check circuit and a control input of the detection circuit and is formed to activate or deactivate the analog signal processing and/or the determination of the digital data by a control signal at the control input of the detection circuit and/or at a control input of the input circuit depending on the at least one test signal.

2. The receiving circuit according to claim 1, wherein the check circuit is configured to compare an address contained in a frame of the digital data with an identification of the node and is configured to output a test signal corresponding to a comparison result of the comparison, and wherein the control circuit is confiugred to output a control signal to deactivate the determination of the digital data in the case of an identity of address and identification.

3. The receiving circuit according to claim 2, wherein the control circuit has a logic and a register connected to the logic, the logic being configured to output the control signal for deactivation for the case of identity based on a register value of the register.

4. The receiving circuit according to claim 3, wherein the register has a register connection for programming at least the register value.

5. The receiving circuit according to claim 3, wherein the deactivation of the determination of the digital data is modifiable exclusively by programming of a register value of the register, and the control circuit is formed in such a way that the deactivation of the determination of the digital data is otherwise independent of a program run implemented in a connected arithmetic logic unit.

6. The receiving circuit according to claim 1, wherein the evaluation circuit has an interface for an arithmetic logic unit, particularly for a computing core of a microcontroller, and wherein the control circuit is confiugred to activate the determination the digital data by a control signal at the control input of the detection circuit based on an interface signal transmitted via the interface.

7. The receiving circuit according to claim 1, wherein the detection circuit has a preamble detector for detecting a preamble in the digital signal.

8. A method for receiving a signal received over an antenna of a node of a radio network, the method comprising:

determining a current frame with digital data from the received signal;

checking the digital data of the current frame;

transmitting, in the case of a positive test result, the digital data of the current frame to an arithmetic logic unit;

deactivating, in the case of the positive test result, an analog signal processing and/or the determination of a following frame; and

reactivating the analog signal processing and/or the determination of a following frame when the current frame is loaded in the arithmetic logic unit.

9. The method according to claim 8, wherein for checking, an address contained in the current frame is compared with an identification of the node, wherein the determination of a following frame is deactivated only when identity of the address and the identification is determined.

10. The method according to claim 8, wherein the comparison of address and identification is turned on and off by a register value.

11. The method according to claim 8, wherein detection of a preamble is stopped to deactivate the determination.

12. Use of a detection circuit and a control circuit in a receiving circuit of a radio network node, deactivating an analog signal processing of a signal received over an antenna of the node and/or a determination of digital data from the signal received over the antenna of the node, when a stored current frame of the digital data has been recognized as valid, and activating the analog signal processing and/or the determination when the transmission of the current frame over an interface of the control circuit has been confirmed, wherein the control circuit is connected to the detection circuit and/or an input circuit for deactivation and activation, and wherein the detection circuit is formed to determine the digital data from the received signal.