Computing Core Application Access Utilizing Dispersed Storage

• US 20130145123A1
• Filed: 01/29/2013
• Published: 06/06/2013
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Grube, Gary W., Markison, Timothy W.
• Granted Patent: US 8,612,796 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module.

Claims

1. A method for execution by a computing core, the method comprises:

receiving a request to fetch an instruction from a processing module of the computing core;

determining whether the instruction is currently stored in main memory of the computing core;

when the instruction is not currently stored in the main memory;

determining whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices;

when the instruction is stored in the DSN memory as the one or more sets of encoded instruction slices, addressing the DSN memory to retrieve the one or more sets of encoded instruction slices;

when at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, decoding the one or more sets of encoded instruction slices using a dispersed storage error coding function to reconstruct the instruction; and

providing the instruction to the processing module.

2. The method of claim 1, wherein the instruction comprises one of:

an operating system instruction;

an application instruction;

a software driver instruction; and

an application programming interface (API) instruction.

3. The method of claim 1, wherein the providing the instruction to the processing module further comprises:

storing the instruction in the main memory prior to the providing.

4. The method of claim 1 comprises, when the instruction is not currently stored in main memory:

identifying a group of instructions to retrieve, wherein the group of instructions includes the instruction;

determining whether the group of instructions is stored in the DSN memory in an error encoded format;

when the group of instructions is stored in the DSN memory in the error encoded format, addressing the DSN memory to retrieve a unique one or more sets of encoded instruction slices for each of the instructions in the group of instructions.

5. The method of claim 1 further comprises:

when the instruction is not currently stored in main memory and is stored in the DSN memory in a non-error encoded format, retrieving a non-error encoded version of the instruction from the DSN memory.

6. The method of claim 1, wherein the DSN memory comprises at least one of:

non-core memory;

local area network (LAN) memory; and

wide area network (WAN) memory.

7. The method of claim 1 further comprises:

determining whether the instruction is an operating system instruction or an application instruction;

when the instruction is the operating system instruction, retrieving the one or more sets of encoded instruction slices from a first DSN memory of the DSN memory; and

when the instruction is the application instruction, retrieving the one or more sets of encoded instruction slices from a second DSN memory of the DSN memory.

8. The method of claim 1 further comprises:

receiving a request from the processing unit to fetch configuration information, wherein the configuration information includes at least one of application configuration parameters regarding an application and user preferences regarding the application;

determining whether the configuration information is currently stored in main memory of the computing core;

when the configuration information is not currently stored in the main memory;

determining whether the configuration information is stored in the DSN memory as one or more sets of encoded configuration slices;

when the configuration information is stored in the DSN memory as the one or more sets of encoded configuration slices, addressing the DSN memory to retrieve the one or more sets of encoded configuration slices;

when at least a threshold number of encoded configuration slices are retrieved for each of the one or more sets of encoded configuration slices, decoding the one or more sets of encoded configuration slices using a dispersed storage error coding function to reconstruct the configuration information; and

providing the configuration information to the processing module.

9. In the method of claim 8 further comprises:

detecting a change in the configuration information;

when a change is detected in the configuration information, updating the configuration information to produce updated configuration information; and

facilitating storage of the updated configuration information in an error encoded format in the DSN memory.

10. A computing core comprises:

a processing module;

main memory; and

a memory controller operable to;

receive a request to fetch an instruction from the processing module;

determine whether the instruction is currently stored in the main memory;

when the instruction is not currently stored in the main memory;

determine whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices;

when the instruction is stored in the DSN memory as the one or more sets of encoded instruction slices, address the DSN memory to retrieve the one or more sets of encoded instruction slices;

when at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, decode the one or more sets of encoded instruction slices using a dispersed storage error coding function to reconstruct the instruction; and

provide the instruction to the processing module.

11. The computing core of claim 10, wherein the instruction comprises one of:

an operating system instruction;

an application instruction;

a software driver instruction; and

an application programming interface (API) instruction.

12. The computing core of claim 10, wherein the memory controller is further operable to:

facilitate storing the instruction in the main memory prior to the providing the instruction to the processing module.

13. The computing core of claim 10, wherein the memory controller is further operable to, when the instruction is not currently stored in main memory:

identify a group of instructions to retrieve, wherein the group of instructions includes the instruction;

determine whether the group of instructions is stored in the DSN memory in an error encoded format;

when the group of instructions is stored in the DSN memory in the error encoded format, address the DSN memory to retrieve a unique one or more sets of encoded instruction slices for each of the instructions in the group of instructions.

14. The computing core of claim 10, wherein the memory controller is further operable to:

when the instruction is not currently stored in main memory and is stored in the DSN memory in a non-error encoded format, retrieve a non-error encoded version of the instruction from the DSN memory.

15. The computing core of claim 10, wherein the DSN memory comprises at least one of:

non-core memory;

local area network (LAN) memory; and

wide area network (WAN) memory.

16. The computing core of claim 10, wherein the memory controller is further operable to:

determine whether the instruction is an operating system instruction or an application instruction;

when the instruction is the operating system instruction, retrieve the one or more sets of encoded instruction slices from a first DSN memory of the DSN memory; and

when the instruction is the application instruction, retrieve the one or more sets of encoded instruction slices from a second DSN memory of the DSN memory.

17. The computing core of claim 10, wherein the memory controller is further operable to:

receive a request from the processing unit to fetch configuration information, wherein the configuration information includes at least one of application configuration parameters regarding an application and user preferences regarding the application;

determine whether the configuration information is currently stored in main memory of the computing core;

when the configuration information is not currently stored in the main memory;

determine whether the configuration information is stored in the DSN memory as one or more sets of encoded configuration slices;

when the configuration information is stored in the DSN memory as the one or more sets of encoded configuration slices, address the DSN memory to retrieve the one or more sets of encoded configuration slices;

when at least a threshold number of encoded configuration slices are retrieved for each of the one or more sets of encoded configuration slices, decode the one or more sets of encoded configuration slices using a dispersed storage error coding function to reconstruct the configuration information; and

provide the configuration information to the processing module.

18. The computing core of claim 17, further comprises:

the processing module operable to;

detect a change in the configuration information;

when a change is detected in the configuration information, update the configuration information to produce updated configuration information; and

the memory controller operable to facilitate storage of the updated configuration information in an error encoded format in the DSN memory.