Computing Core Application Access Utilizing Dispersed Storage

• US 20130145232A1
• Filed: 01/29/2013
• Published: 06/06/2013
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Grube, Gary W., Markison, Timothy W.
• Granted Patent: US 8,621,265 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to store a data result from a processing module and determines whether to store the data result in an error encoded format. When the memory controller determines to store the data result in the error encoded format, it facilitates encoding the data result in accordance with a dispersed storage error coding function to produce one or more sets of encoded data slices. The memory controller then determines where to store the one or more sets of encoded data slices and provides the one or more sets of encoded data slices to one or more identified memories for storage.

Claims

1. A method for execution by a computer core, the method comprises:

receiving a request to store a data result from a processing module;

determining whether to store the data result in an error encoded format;

when the data result is to be stored in the error encoded format;

facilitating encoding the data result in accordance with a dispersed storage error coding function to produce one or more sets of encoded data slices;

determining where to store the one or more sets of encoded data slices; and

providing the one or more sets of encoded data slices to one or more identified memories for storage.

2. The method of claim 1, wherein the determining whether to store the data result in an error encoded format comprises:

accessing a memory map to determine that the data result is to be stored in the error encoded format.

3. The method of claim 1, wherein the determining where to store the one or more sets of encoded data slices comprises:

accessing a memory map to determine the one or more identified memories.

4. The method of claim 1 further comprises:

when the data result is to be stored in a non-error encoded format;

determining where to store the data result; and

providing the data result to an identified memory for storage.

5. The method of claim 1, wherein the data result comprises one of:

a data result from executing one or more operating system instructions;

a data result from executing one or more application instructions; and

a data result from executing one or more software driver instructions.

6. The method of claim 1, wherein the one or more identified memories comprises one or more of:

main memory;

non-core memory;

local area network (LAN) memory; and

wide area network (WAN) memory.

7. The method of claim 1 further comprises:

initially storing the data result in main memory in a non-error encoded format; and

retrieving the data result from the main memory for the encoding.

8. The method of claim 1, wherein the facilitating encoding comprises:

buffering the data result;

when the processing module is available, sending the data result and encoding instructions to the processing module;

executing, by the processing module, the encoding instructions to error encode the data result to produce the one or more sets of encoded data slices; and

receiving the one or more sets of encoded data slices from the processing module.

9. A computing core comprises:

a processing module;

main memory; and

a memory controller operable to;

receive a request to store a data result from a processing module;

determine whether to store the data result in an error encoded format;

when the data result is to be stored in the error encoded format;

facilitate encoding the data result in accordance with a dispersed storage error coding function to produce one or more sets of encoded data slices;

determine where to store the one or more sets of encoded data slices; and

provide the one or more sets of encoded data slices to one or more identified memories for storage.

10. The computing core of claim 9, wherein the memory controller is further operable to determine whether to store the data result in an error encoded format by:

accessing a memory map to determine that the data result is to be stored in the error encoded format.

11. The computing core of claim 9, wherein the memory controller is further operable to determine where to store the one or more sets of encoded data slices by:

accessing a memory map to determine the one or more identified memories.

12. The computing core of claim 9, wherein the memory controller is further operable to:

when the data result is to be stored in a non-error encoded format;

determine where to store the data result; and

provide the data result to an identified memory for storage.

13. The computing core of claim 9, wherein the data result comprises one of:

a data result from executing one or more operating system instructions;

a data result from executing one or more application instructions; and

a data result from executing one or more software driver instructions.

14. The computing core of claim 9, wherein the one or more identified memories comprises one or more of:

the main memory;

non-core memory;

local area network (LAN) memory; and

wide area network (WAN) memory.

15. The computing core of claim 9, wherein the memory controller is further operable to:

facilitate initially storing the data result in main memory in a non-error encoded format; and

retrieve the data result from the main memory for the encoding.

16. The computing core of claim 9 further comprises:

the memory controller is further operable to facilitate the encoding by;

buffering the data result;

when the processing module is available, sending the data result and encoding instructions to the processing module;

the processing module is operable to execute the encoding instructions to error encode the data result to produce the one or more sets of encoded data slices; and

the memory controller is further operable to receive the one or more sets of encoded data slices from the processing module.