EMBEDDED SYSTEMS AND METHODS FOR THREADS AND BUFFER MANAGEMENT THEREOF

• US 20130145372A1
• Filed: 07/16/2012
• Published: 06/06/2013
• Est. Priority Date: 12/01/2011
• Status: Active Grant

• Current Assignee: Institute For Information Industry
• Original Assignee: Institute For Information Industry
• Inventors: YEN, Chun-Tai, LIU, Hsin-Yi, KAO, Chih-Chiang, PAN, Cheng-Hung
• Granted Patent: US 9,239,742 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

Embedded systems are provided, which includes a processing unit and a memory. The processing unit simultaneously executes first thread having a flag for performing a data acquisition operation and second thread for performing a data process and output operation for the acquired data in the data acquisition operation. The flag is used for indicating whether a state of the first thread is in an execution state or a sleep state. The memory which is coupled to the processing unit provides a shared buffer for the first and second threads. Before executing the second thread, the flag is checked to determine whether to execute the second thread, wherein the second thread is executed when the flag indicates the sleep state while execution of the second thread is suspended when the flag indicates the execution state.

Claims

1. An embedded system, comprising:

a processing unit, simultaneously executing at least one first thread having a flag for performing a data acquisition operation and one second thread for performing a data process and output operation for acquired data in the data acquisition operation, wherein the flag is used for indicating that a state of the first thread is in one of an execution state and a sleep state; and

a memory coupled to the processing unit, providing a shared buffer for the at least one first thread and the second thread,

wherein, the processing unit checks the flag before executing the second thread, wherein the second thread is executed when the flag indicates the sleep state while execution of the second thread is suspended when the flag indicates the execution state.

2. The embedded system of claim 1, further comprising:

a timer, recording next execution time for the first thread;

wherein the processing unit executes the first thread and sets the flag to indicate the execution state according to the next execution time for the first thread recorded by the timer while the processing unit sets the flag to indicate the sleep state and updates the next execution time for the first thread recorded by the timer after the execution of the first thread is finished.

3. The embedded system of claim 1, wherein when the flag indicates the execution state and the execution of the second thread is suspended, the processing unit further returns to execute the second thread when the flag is changed to the sleep state.

4. The embedded system of claim 2, wherein the processing unit further executes the second thread until next execution time for the first thread of the timer is reached when the flag indicates the sleep state.

5. The embedded system of claim 1, further comprising:

a bus; and

an integrated circuit for buffer management coupled to the memory and the processing unit through the bus, accessing the shared buffer, acquiring data from the shared buffer and writing the acquired data in the data acquisition operation to an external storage unit, and acquiring data from the external storage unit and writing the data acquired from the external storage unit to the shared buffer.

6. The embedded system of claim 5, wherein the integrated circuit for buffer management further comprises:

a direct memory access (DMA) controller, generating an operation signal according to a usage status of the shared buffer and performing a DMA operation on the shared buffer through the bus; and

a microcontroller coupled to the DMA controller and the external storage unit, accessing the external storage unit according to the operation signal;

wherein the DMA operation is for acquiring data from the shared buffer and the microcontroller writes the data acquired from the shared buffer to the external storage unit when the operation signal is a data acquisition signal; and

the DMA operation is for acquiring data from the external storage unit and the microcontroller writes the data acquired from the external storage unit to the shared buffer when the operation signal is a data storing signal.

7. The embedded system of claim 6, wherein the shared buffer is further divided into a first buffer regarding as a buffer of the first thread and a second buffer regarding as a buffer of the second thread.

8. The embedded system of claim 7, wherein the first buffer further includes a plurality of blocks and the second buffer further includes a plurality of blocks, wherein when the usage status of the shared buffer indicates that one dedicated block of the blocks within the first buffer is full, the DMA controller generates the data acquisition signal and acquires data from the first buffer and the microcontroller writes the data acquired from the first buffer to the external storage unit;

and when the usage status of the shared buffer indicates that one dedicated block of the blocks within the second buffer is empty, the DMA controller generates the data acquisition signal and the microcontroller acquires data from the external storage unit, and the DMA controller writes the data acquired from the external storage unit to the second buffer.

9. The embedded system of claim 7, wherein when the usage status of the shared buffer indicates that the usage of the first buffer has exceeded a dedicated ratio for the first buffer, the DMA controller generates the data acquisition signal and acquires the data of the first buffer and the microcontroller writes the acquired data of the first buffer to the external storage unit;

and when the usage status of the shared buffer indicates that the usage of the second buffer has lower than a dedicated ratio for the second buffer, the DMA controller generates the data storing signal and the microcontroller acquires data from the external storage unit, and the DMA controller writes the data acquired from the external storage unit to the second buffer.

10. A method for thread and buffer management for use in an embedded system, wherein the embedded system simultaneously executes at least one first thread for performing a data acquisition operation and one second thread for performing a data process and output operation for the acquired data in the data acquisition operation, wherein a shared buffer is provided to the first and second threads, the method comprising:

providing the first thread a flag for indicating that a state of the first thread is in one of an execution state and a sleep state; and

checking the flag before executing the second thread, wherein the second thread is executed when the flag indicates the sleep state while execution of the second thread is suspended when the flag indicates the execution state.

11. The method of claim 10, further comprising:

providing a timer for recording next execution time for the first thread;

executing the first thread and setting the flag to indicate the execution state according to the next execution time for the first thread recorded by the timer; and

setting the flag to indicate the sleep state and updating the next execution time for the first thread recorded by the timer after the execution of the first thread is finished.

12. The method of claim 10, wherein the step of checking the flag to determine whether to execute the second thread further comprises:

when the flag indicates the execution state and the execution of the second thread is suspended, returning to execute the second thread when the flag is changed to the sleep state.

13. The method of claim 11, wherein the step of checking the flag to determine whether to execute the second thread further comprises:

executing the second thread until next execution time for the first thread of the timer is reached when the flag indicates the sleep state.

14. The method of claim 10, wherein the embedded system further includes a integrated circuit for buffer management and an external storage unit, and the method further comprises:

accessing, by the integrated circuit for buffer management, the shared buffer, acquiring data from the shared buffer and writing the acquired data in the data acquisition operation to the external storage unit, and acquiring data from the external storage unit and writing the data acquired from the external storage unit to the shared buffer.

15. The method of claim 14, wherein the step of accessing, by the integrated circuit for buffer management, the shared buffer further comprises:

generating an operation signal according to a usage status of the shared buffer and performing a DMA operation on the shared buffer through the bus, thereby accessing the external storage unit according to the operation signal;

wherein the DMA operation is for acquiring data from the shared buffer and writing the data acquired from the shared buffer to the external storage unit through the bus when the operation signal is a data acquisition signal; and

the DMA operation is for acquiring data from the external storage unit and writing the data acquired from the external storage unit to the shared buffer when the operation signal is a data storing signal.