FIELD EFFECT TRANSISTOR USING OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME

• US 20130146452A1
• Filed: 02/07/2013
• Published: 06/13/2013
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Idemitsu Kosan Company Limited
• Original Assignee: Idemitsu Kosan Company Limited
• Inventors: YANO, Koki, INOUE, Kazuyoshi, TOMAI, Shigekazu, KASAMI, Masashi, KAWASHIMA, Hirokazu
• Granted Patent: US 8,981,369 B2
• Time in Patent Office: Days
• US Class Current: 204/298.13
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A field effect transistor which includes, on a substrate, at least a semiconductor layer, a passivation layer for the semiconductor layer, a source electrode, a drain electrode, a gate insulating film and a gate electrode, the source electrode and the drain electrode being connected through the semiconductor layer, the gate insulating film being present between the gate electrode and the semiconductor layer, the passivation layer being at least on one surface side of the semiconductor layer, and the semiconductor layer including a composite oxide which comprises In (indium), Zn (zinc) and Ga (gallium) in the following atomic ratios (1) to (3):

In/(In+Zn)=0.2 to 0.8   (1)

In/(In+Ga)=0.59 to 0.99   (2)

Zn/(Ga+Zn)=0.29 to 0.99   (3).

Claims

1-15. -15. (canceled)

16. A composite oxide comprising In (indium), Zn (zinc) and Ga (gallium) in the following atomic ratios (1) to (3):

In/(In+Zn)=0.2 to 0.8  

 

(1)

In/(In+Ga)=0.59 to 0.99  

 

(2)

In/(Ga+Zn)=0.29 to 0.99  

 

(3),

forming a sintered target from an oxide semiconductor.

17. The composite oxide according to claim 16, having the following atomic ratio (4):

Ga/(In+Zn+Ga)=0.1 to 0.2  

 

(4).

18. The composite oxide according to claim 16, having the following atomic ratio:

Ga/(In+Zn+Ga)=−

/01 to 0.05/

19. The composite oxide according to claim 16, having the following atomic ratio:

Ga/(In+Zn+Ga)=0.05 to 0.2.

20. The composite oxide according to claim 16, having the following atomic ratio (5) or the following atomic ratio (6):

In/(In+Zn+Ga)=0.3 to 0.5  

 

5;

In/(In+Zn+Ga)=0.5 to 0.7, 0.5 not included.  

 

6;

21. The composite oxide according to claim 16, further comprising one or more lements of Sn (tin), Ge (germanium), Si (silicon), Ti (titanium), Zr (zirconium) or Hf (hafnium) in an amount of 100 to 10,000 atomic ppm.

22. The composite oxide according to claim 16, wherein the bulk resistance of the target is less than 20 mΩ

cm.