FIELD EFFECT TRANSISTOR

• US 20130146868A1
• Filed: 12/10/2012
• Published: 06/13/2013
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: E Ink Holdings Incorporated
• Original Assignee: E Ink Holdings Incorporated
• Inventors: ZAN, Hsiao-Wen, LIAO, Chun-Hung
• Granted Patent: US 9,236,494 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor (FET) is provided. The active layer of this FET is composed of at least two different amorphous metal oxide semiconductor layer stacked together. Therefore, the two opposite surfaces of the active layer can have different band gap values.

Claims

1. A field effect transistor, comprising:

a gate;

a gate insulating layer;

an active layer having a first surface and a second surface opposite to the first surface, wherein the gate, the gate insulating layer and the active layer are sequentially stacked on a substrate, the active layer has at least two different metal oxide semiconductor layers, and a first band gap value at the first surface and a second band gap value at the second surface are different; and

a source and a drain respectively connecting to the active layer.

2. The field effect transistor of claim 1, wherein a difference between the first band gap value and the second band gap value are at least 0.5 eV.

3. The field effect transistor of claim 1, wherein a difference between the first band gap value and the second band gap value are at least 1 eV.

4. The field effect transistor of claim 1, wherein the first band gap value at the first surface is gradually changed to the second band gap value at the second surface of the active layer.

5. The field effect transistor of claim 1, wherein materials of the two different metal oxide semiconductor layers are selected from a group consisting of indium gallium zinc oxide (IGZO) indium gallium oxide (IGO) indium zinc oxide (IZO) zinc oxide (ZnO) calcium oxide (CaO) magnesium oxide (MgO) aluminum oxide (Al₂O₃), indium xoide (In₂O₅), gallium oxide (GaO₂), titanium oxide (TiO₂), zirconium oxide (ZrO₂), and silicon oxide (SiO_x).

6. The field effect transistor of claim 1, further comprising a third metal oxide semiconductor layer located between the two different metal oxide semiconductor layers, and a third band gap value of the third metal oxide semiconductor layer is also between the first band gap value and the second band gap value.

7. The field effect transistor of claim 6, wherein a material of the third metal oxide semiconductor layer is selected from a group consisting of indium gallium zinc oxide (IGZO) indium gallium oxide (IGO) indium zinc oxide (IZO) zinc oxide (ZnO) calcium oxide (CaO) magnesium oxide (MgO) aluminum oxide (Al₂O₃), indium xoide (In₂O₅), gallium oxide (GaO₂), titanium oxide (TiO₂), zirconium oxide (ZrO₂), and silicon oxide (SiO_x).

8. The field effect transistor of claim 1, wherein the gate, the source and the drain are located on the same side of the active layer.

9. The field effect transistor of claim 1, wherein the gate is located on one side of the active layer, and the source and the drain are located on the opposite side of the active layer.

10. The field effect transistor of claim 1, wherein the metal oxide semiconductor layers are amorphous.