Trench-Gate Resurf Semiconductor Device and Manufacturing Method

• US 20130146967A1
• Filed: 10/24/2012
• Published: 06/13/2013
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven Thomas, Rutter, Phil
• Granted Patent: US 9,006,822 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Claims

1. A trench-gate semiconductor device, comprising:

a drain contact;

a silicon semiconductor body over the drain contact which is doped with a first type of dopant;

a gate trench formed in the top of the semiconductor body;

a gate dielectric lining the gate trench;

a gate electrode formed in the gate trench;

source regions formed in the semiconductor body on opposite sides of the gate trench, separated from the gate electrode by the gate dielectric; and

an implant well on each side of the gate trench, doped with a second type of dopant, of opposite polarity type to the first type of dopant of the semiconductor body, and extending more deeply into the semiconductor body than the gate trench,

wherein the device further comprises a pillar region extending downwardly from the bottom of the gate trench and which is electrically connected to the source regions, doped with the second type of dopant beneath the gate trench between the implant wells.

2. A device as claimed in claim 1, further comprising:

a contact region to the source regions, comprising a moat formed around the source regions extending into the top of the semiconductor body.

3. A device as claimed in claim 1, wherein the pillar region has a width of between 0.7 and 1.0 times the width of the gate trench.

4. A device as claimed in claim 1, wherein the pillar region extends to a depth which is substantially equal to the depth of the implant wells.

5. A device as claimed in claim 1, wherein the semiconductor body is doped n-type, the implant wells and the pillar region are doped p-type.

6. A device as claimed in claim 1, wherein the pillar region is electrically connected to the source regions.

13. A device as claimed in claim 1, wherein an additional implant connects the pillar region to the implant well.

14. A device as claimed in claim 13, wherein the additional implant is provided at the ends of the gate trench and comprises the second type of dopant.

7. A method of manufacturing a trench-gate semiconductor device, comprising:

forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region;

etching a gate trench into the substrate;

forming a gate oxide against at least the side walls of the trench and forming a thicker gate oxide at the bottom of the trench;

implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant, the pillar region extending downwardly from the bottom of the gate trench;

depositing, doping and annealing a gate electrode in the gate trench;

implanting and annealing a semiconductor body region on each side of the gate trench;

implanting and annealing source regions on each side of the gate trench over the semiconductor body region;

etching the semiconductor body region to form a moat region at the sides of the source regions to form contact openings for contact with the source regions;

implanting and annealing RESURF regions at the base of the moat; and

depositing and patterning a metallisation layer to form source and gate contacts,

wherein the pillar region is electrically connected to the source regions.

8. A method as claimed in claim 7, wherein the pillar region is formed with a width of between 0.7 and 1.0 times the width of the gate trench.

9. A method as claimed in claim 7, wherein the pillar region is formed to a depth which is substantially equal to the depth of the implant wells.

10. A method as claimed in claim 7, wherein the semiconductor body is doped n-type, the implant wells and the pillar region are doped p-type.

11. A method as claimed in claim 7, further comprising forming an implant region of the second type of dopant at the ends of the gate trench which couples the pillar region to the RESURF regions.

12. A method as claimed in claim 7, further comprising depositing and patterning a metallisation layer on the opposite side of the substrate to the source and gate contacts, to form a drain contact.