POST-PASSIVATION INTERCONNECT STRUCTURE

• US 20130147033A1
• Filed: 12/07/2011
• Published: 06/13/2013
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Hsien-Wei, TSAI, Hao-Yi, LII, Mirng-Ji, YU, Chen-Hua
• Granted Patent: US 9,613,914 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02235 Reinforcing structures
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a passivation layer overlying the semiconductor substrate;

an interconnect structure overlying the passivation layer, the interconnect structure comprising a landing pad region and a dummy region electrically separated from each other;

a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region;

a metal layer formed on the exposed portion of landing pad region and the exposed portion of the dummy region; and

a bump formed on the metal layer overlying the landing pad region.

2. The semiconductor device of claim 1, wherein the metal layer formed in the second opening of the protective layer is a dummy pillar electrically separated from the bump.

3. The semiconductor device of claim 1, wherein the metal layer comprises at least one of a titanium layer, a copper layer, or a nickel layer.

4. The semiconductor device of claim 1, wherein the interconnect structure comprises a copper layer.

5. The semiconductor device of claim 1, wherein the interconnect structure comprises a plurality of dummy regions adjacent to the landing pad region.

6. The semiconductor device of claim 1, wherein the protective layer comprises a plurality of second openings adjacent to the first opening, and the metal layer fills the plurality of second openings to form a plurality of dummy pillars.

7. The semiconductor device of claim 1, wherein the first protective layer comprises polymer.

8. The semiconductor device of claim 1, further comprising a polymer layer formed between the passivation layer and the interconnect structure.

10. The semiconductor device of claim 1, further comprising a conductive pad formed on the semiconductor substrate, wherein the conductive pad is partially covered by the passivation layer, and the conductive pad is electrically connected to the landing pad region of the interconnect structure.

11. The semiconductor device of claim 10, further comprising a dummy pad formed on the semiconductor substrate and electrically separated from the conductive pad, wherein the dummy pad is partially covered by the passivation layer, and the dummy pad is electrically connected to the dummy region of the interconnect structure.

12. The semiconductor device of claim 11, wherein the conductive pad and the dummy pad are formed of the same material.

13. A semiconductor device, comprising:

a semiconductor substrate comprising a conductive pad;

a passivation layer formed on the semiconductor substrate and exposing a portion of the conductive pad;

a post-passivation interconnect (PPI) structure overlying the passivation layer and comprising a first region electrically connected to the exposed portion of the conductive pad, and a second region electrically separated from the first region;

a polymer layer overlying the PPI structure and comprising a first opening exposing a portion of the first region of the PPI structure and a second opening exposing a portion of the second region of the PPI structure; and

an under-bump-metallization (UBM) layer formed in the first opening of the polymer layer; and

a metal layer formed in the second opening of the polymer layer.

14. The semiconductor device of claim 13, wherein the semiconductor substrate comprises a dummy pad electrically separated from the conductive pad, the passivation layer exposes a portion of the dummy pad, and the second region of the PPI structure is formed over the exposed portion of the dummy pad.

15. The semiconductor device of claim 13, wherein the PPI structure comprises a plurality of second regions adjacent to the first region.

16. The semiconductor substrate of claim 15, wherein the polymer layer comprises a plurality of second openings exposing the plurality of second regions of the PPI structure respectively.

17. The semiconductor substrate of claim 16, wherein the metal layer fills the plurality of second openings of the polymer layer.

18. The semiconductor device of claim 13, wherein the metal layer comprises at least one of a titanium layer, a copper layer, or a nickel layer.

19. The semiconductor device of claim 13, further comprising another polymer layer between the passivation layer and the PPI structure.

20. The semiconductor device of claim 13, wherein the UBM layer and the metal layer are formed of the same material layer.