METHOD AND APPARATUS FOR POWER SWITCHING

• US 20130147423A1
• Filed: 12/07/2012
• Published: 06/13/2013
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: SUTARDJA, Pantas, SIGUENZA, Oscar M., JIANG, Bin, CHAO, Hsien-Chih, TRIVEDI, Devang
• Granted Patent: US 9,614,386 B2
• Time in Patent Office: Days
• US Class Current: 320/107
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Aspects of the disclosure provide a circuit. The circuit includes a switch and a switch controller. The switch is between a first node that receives a first power supply and a second node, and is controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node. The switch controller is configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply.

Claims

1. A circuit, comprising:

a switch between a first node that receives a first power supply and a second node, the switch being controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node; and

a switch controller configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply.

2. The circuit of claim 1, wherein the switch controller is configured to generate the switch control signal to control a first charging current flowing through the switch during a first time duration and control a second charging current flowing through the switch during a second time duration to switch on the second power supply.

3. The circuit of claim 1, wherein the switch controller is coupled with the switch in a current mirror to control the charging current.

4. The circuit of claim 1, wherein the switch control signal is an analog signal.

5. The circuit of claim 4, wherein the switch controller is configured to generate the switch control signal in response to digital control signals from a power controller.

6. The circuit of claim 1, wherein the switch is a distributed switch that includes a plurality of sub-switches distributed in the circuit.

7. The circuit of claim 6, wherein each sub-switch includes a plurality of P-type metal-oxide-semiconductor field effect transistors coupled together in parallel.

8. The circuit of claim 1, further comprising:

functional circuits configured to operate when the second power supply is switched on.

9. A method, comprising:

generating a switch control signal in response to a control signal;

providing the switch control signal to a switch between a first node that receives a first power supply and a second node; and

controlling a charging current flowing through the switch to switch on a second power supply at the second node.

10. The method of claim 9, wherein controlling the charging current flowing through the switch to switch on the second power supply further comprises:

controlling a first charging current flowing through the switch when the control signal is indicative of a first charging mode; and

controlling a second charging current flowing through the switch when the control signal is indicative of a second charging mode.

11. The method of claim 9, wherein controlling the charging current flowing through the switch to switch on the second power supply further comprises:

mirroring the charging current with a reference current.

12. The method of claim 9, wherein providing the switch control signal to the switch between the first node that receives the first power supply and the second node further comprises:

providing the switch control signal to a plurality of distributed switches.

13. The method of claim 9, wherein generating the switch control signal in response to the control signal further comprises:

generating the switch control signal in analog in response to the control signal in digital.

14. An integrated circuit (IC) chip, comprising:

a power controller configured to generate a control signal to a circuit block; and

the circuit block that includes;

a switch between a first node that receives a first power supply and a second node, the switch being controlled to couple/decouple the second node with the first node to switch on/off the second power supply; and

a switch controller configured to generate a switch control signal in response to the control signal to control a charging current flowing through the switch to switch on the second power supply.

15. The IC chip of claim 14, wherein the switch controller is configured to generate the switch control signal to control a first charging current flowing through the switch during a first time duration and control a second charging current flowing through the switch during a second time duration to switch on the second power supply.

16. The IC chip of claim 14, wherein the switch controller is coupled with the switch in a current mirror to control the charging current.

17. The IC chip of claim 14, wherein the switch control signal is an analog signal.

18. The IC chip of claim 14, wherein the switch is a distributed switch that includes a plurality of sub-switches distributed in the circuit block.

19. The IC chip of claim 18, wherein each sub-switch includes a plurality of P-type metal-oxide-semiconductor field effect transistors coupled together in parallel.

20. The IC chip of claim 14, wherein the circuit block further comprises:

functional circuits configured to operate when the second power supply is switched on.