ADAPTIVE DEAD-TIME CONTROL
First Claim
1. A DC-to-DC converter comprising:
- first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load;
a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor, wherein the first edge of the second signal corresponds to a first edge of one of the PWM pulses;
a second timing module that determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor, wherein the second edge of the second signal corresponds to a second edge of the one of the PWM pulses; and
a delay module that delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and that delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference.
1 Assignment
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Accused Products
Abstract
A DC-to-DC converter includes first and second transistors that are connected in series between a supply voltage and ground and that are driven by PWM pulses. A junction of the transistors is connected to an inductance that is connected in series to a load. A first timing module determines a first time difference between a first edge of a first signal at the junction and a first edge of a second signal at a control terminal of the first transistor. A second timing module determines a second time difference between a second edge of the first signal and a second edge of the second signal. The first and second edges of the second signal respectively correspond to first and second edges of one of the PWM pulses. A delay module delays the first and second edges of the second signal respectively based on the first and second time differences.
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Citations
34 Claims
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1. A DC-to-DC converter comprising:
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first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load; a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor, wherein the first edge of the second signal corresponds to a first edge of one of the PWM pulses; a second timing module that determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor, wherein the second edge of the second signal corresponds to a second edge of the one of the PWM pulses; and a delay module that delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and that delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A DC-to-DC converter comprising:
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first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load; a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the second transistor, wherein the first edge of the second signal corresponds to a first edge of one of the PWM pulses; a second timing module that determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the second transistor, wherein the second edge of the second signal corresponds to a second edge of the one of the PWM pulses; and a delay module that delays the first edge of the second signal at the control terminal of the second transistor based on the first time difference and that delays the second edge of the second signal at the control terminal of the second transistor based on the second time difference. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A DC-to-DC converter comprising:
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first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load; a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor, wherein the first edge of the second signal corresponds to a first edge of one of the PWM pulses; a second timing module that determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor, wherein the second edge of the second signal corresponds to a second edge of the one of the PWM pulses; a third timing module that determines a third time difference between the first edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor, wherein the first edge of the third signal corresponds to the first edge of the one of the PWM pulses; a first delay module that delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and that delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference; and a second delay module that delays the first edge of the third signal at the control terminal of the second transistor based on the third time difference and that does not delay a second edge of the third signal at the control terminal of the second transistor, wherein the second edge of the third signal corresponds to the second edge of the one of the PWM pulses. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A DC-to-DC converter comprising:
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first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load; a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor, wherein the first edge of the second signal corresponds to a first edge of the one of the PWM pulses; a second timing module that determines a second time difference between the first edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor, wherein the first edge of the third signal corresponds to the first edge of the one of the PWM pulses; a third timing module that determines a third time difference between a second edge of the first signal at the node and a second edge of the third signal at the control terminal of the second transistor, wherein the second edge of the third signal corresponds to a second edge of the one of the PWM pulses; a first delay module that delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and that does not delay a second edge of the second signal at the control terminal of the first transistor, wherein the second edge of the second signal corresponds to the second edge of the one of the PWM pulses; and a second delay module that delays the first edge of the third signal at the control terminal of the second transistor based on the second time difference and that delays the second edge of the third signal at the control terminal of the second transistor based on the third time difference. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A DC-to-DC converter comprising:
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first and second transistors each driven by pulse-width modulated (PWM) pulses and each having first and second terminals and a control terminal, wherein the first terminal of the first transistor is connected to a supply voltage, the second terminal of the first transistor and the first terminal of the second transistor are connected to a node, the second terminal of the second transistor is connected to ground, and the node is connected to an inductance that is connected in series to a load; a first timing module that determines a first time difference between a first edge of a first signal at the node and a first edge of a second signal at the control terminal of the first transistor, wherein the first edge of the second signal corresponds to a first edge of one of the PWM pulses; a second timing module that determines a second time difference between a second edge of the first signal at the node and a second edge of the second signal at the control terminal of the first transistor, wherein the second edge of the second signal corresponds to a second edge of the one of the PWM pulses; a third timing module that determines a third time difference between the second edge of the first signal at the node and a first edge of a third signal at the control terminal of the second transistor, wherein the first edge of the second signal corresponds to the second edge of the one of the PWM pulses; a fourth timing module that determines a fourth time difference between the first edge of the first signal at the node and a second edge of the third signal at the control terminal of the second transistor, wherein the second edge of the third signal corresponds to the first edge of the one of the PWM pulses; a first delay module that delays the first edge of the second signal at the control terminal of the first transistor based on the first time difference and that delays the second edge of the second signal at the control terminal of the first transistor based on the second time difference; and a second delay module that delays the first edge of the third signal at the control terminal of the second transistor based on the third time difference and that delays the second edge of the third signal at the control terminal of the second transistor based on the fourth time difference. - View Dependent Claims (30, 31, 32, 33, 34)
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Specification