LOGIC CIRCUIT

• US 20130147519A1
• Filed: 02/07/2013
• Published: 06/13/2013
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOYAMA, Jun, AKIMOTO, Kengo, TSUBUKU, Masashi
• Granted Patent: US 9,083,334 B2
• Time in Patent Office: Days
• US Class Current: 326/102
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/09407 of the same canal type
• CPC Class Codes: H03K 19/09421 Diode field-effect transistor logic H03K19/0956, H03K19/096 take precedence
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Claims

1. A semiconductor device comprising:

a logic circuit comprising;

a first transistor comprising a first gate electrode, a first electrode, and a second electrode;

a second transistor comprising a second gate electrode, the second electrode, and a third electrode;

a first terminal electrically connected to the second gate electrode; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to the first electrode;

wherein a low power supply voltage terminal is electrically connected to the third electrode,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

the first electrode which is electrically connected to the first oxide semiconductor layer; and

the second electrode which is electrically connected to the first oxide semiconductor layer,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the gate insulating layer;

the second electrode which is electrically connected to the second oxide semiconductor layer; and

the third electrode which is electrically connected to the second oxide semiconductor layer,

wherein a layer comprising oxygen and comprising silicon or aluminum is on the second oxide semiconductor layer, and

wherein a resistance of the second oxide semiconductor layer is lower than a resistance of the first oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the second transistor comprises an oxygen vacancy control region between the second electrode and the third electrode over a surface of the second oxide semiconductor layer, the surface being opposite to a surface in contact with the gate insulating layer.

3. A semiconductor device comprising:

a logic circuit comprising;

a first transistor comprising a first gate electrode, a first electrode, and a second electrode;

a second transistor comprising a second gate electrode, the second electrode, and a third electrode;

a first terminal electrically connected to the second gate electrode; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to the first electrode;

wherein a low power supply voltage terminal is electrically connected to the third electrode,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

the first electrode which is electrically connected to the first oxide semiconductor layer; and

the second electrode which is electrically connected to the first oxide semiconductor layer,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the gate insulating layer;

the second electrode which is electrically connected to the second oxide semiconductor layer; and

the third electrode which is electrically connected to the second oxide semiconductor layer,

wherein a layer comprising oxygen and comprising silicon or aluminum is on the second oxide semiconductor layer,

wherein a resistance of the second oxide semiconductor layer is lower than a resistance of the first oxide semiconductor layer, and

wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 3, wherein the second transistor comprises an oxygen vacancy control region between the second electrode and the third electrode over a surface of the second oxide semiconductor layer, the surface being opposite to a surface of the second oxide semiconductor layer in contact with the gate insulating layer.

5. A display device comprising:

a pixel portion;

a driver circuit comprising a logic circuit;

the logic circuit comprising;

a first transistor comprising a first gate electrode, a first electrode, and a second electrode;

a second transistor comprising a second gate electrode, the second electrode, and a third electrode;

a first terminal electrically connected to the second gate electrode; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to the first electrode;

wherein a low power supply voltage terminal is electrically connected to the third electrode,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

the first electrode which is electrically connected to the first oxide semiconductor layer; and

the second electrode which is electrically connected to the first oxide semiconductor layer,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the gate insulating layer;

the second electrode which is electrically connected to the second oxide semiconductor layer; and

the third electrode which is electrically connected to the second oxide semiconductor layer,

wherein a layer comprising oxygen and comprising silicon or aluminum is on the second oxide semiconductor layer, and

wherein a resistance of the second oxide semiconductor layer is lower than a resistance of the first oxide semiconductor layer.

6. The display device according to claim 5, wherein the second transistor comprises an oxygen vacancy control region between the second electrode and the third electrode over a surface of the second oxide semiconductor layer, the surface being opposite to a surface of the second oxide semiconductor layer in contact with the gate insulating layer.