NEAR-INTEGER CHANNEL SPUR MITIGATION IN A PHASE-LOCKED LOOP
First Claim
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1. A method comprising:
- relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path when there is a near-integer relationship between the reference clock frequency input and the output frequency; and
filtering the spur frequency component through the phase-locked loop.
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Abstract
A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.
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Citations
20 Claims
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1. A method comprising:
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relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path when there is a near-integer relationship between the reference clock frequency input and the output frequency; and filtering the spur frequency component through the phase-locked loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A phase-locked loop comprising:
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a phase detector configured to receive a reference clock frequency input, a count value of a number of clock cycles of an output frequency of the phase-locked loop and a fractional count value associated with a fractional number of clock cycles of the output frequency, to sample the count value and the fractional count value at every clock cycle of the reference clock frequency input, to calculate a difference between the sampled count value and an expected count value derived from a relation between the output frequency and the reference clock frequency input, and to output a phase error associated with the difference therebetween; a divider, coupled to the phase detector and configured to operate on the output frequency, to generate a divided frequency component of the output frequency, to count clock cycles associated with the output frequency, and to feed the count value to the phase detector; a clock gating circuit, coupled to the divider and configured to enable gating of at least one clock cycle of the output frequency configured to be operated on by the divider during every clock cycle of the reference clock frequency input when there is a near-integer relationship between the output frequency and the reference clock frequency input through a clock gating signal generated therein, wherein the gating is configured to effect relocation of a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of the divided frequency component with the reference clock frequency input to a frequency outside the cut-off frequency of the phase-locked loop through speeding up a phase variation of the divided frequency component with respect to the reference clock frequency input at successive zero-crossings thereof; a loop filter configured to receive the phase error from the phase detector, to generate a control signal based on the phase error, and to filter the spur frequency component; and a control oscillator configured to control the output frequency of the phase-locked loop based on the control signal from the loop filter, the control oscillator being coupled to the clock gating circuit and the fractional count value being obtained through processing the output frequency from the control oscillator. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A circuit comprising:
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a delay logic configured to receive a re-sampled version of a reference clock frequency input to a phase-locked loop and to delay the re-sampled version by at least one clock cycle of an output frequency of the phase-locked loop, a divided frequency component of which is configured to be fed back as another input thereto, the at least one clock cycle being configured to be an odd number, wherein the re-sampled version is generated through a re-sampling logic, associated with the phase-locked loop and configured to re-sample the reference clock frequency input with one of a falling edge and a rising edge of the output frequency; and a pulse generation logic configured to generate a clock gating signal based on the re-sampled version of the reference clock frequency input and the delayed re-sampled version thereof, wherein the clock gating signal is configured to change to a second constant state thereof for a time interval corresponding to the delay between the re-sampled version of the reference clock frequency input and the delayed re-sampled version thereof within every clock cycle of the reference clock frequency input from a first constant state corresponding to all other time intervals therein, wherein the clock gating signal is further configured to enable gating of the at least one clock cycle of the output frequency of the phase-locked loop during every clock cycle of the reference clock frequency input when there is a near-integer relationship between the output frequency and the reference clock frequency input, and wherein the gating is configured to effect relocation of a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of the divided frequency component of the output frequency with the reference clock frequency input to a frequency outside the cut-off frequency of the phase-locked loop through speeding up a phase variation of the divided frequency component with respect to the reference clock frequency input at successive zero-crossings thereof. - View Dependent Claims (19, 20)
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Specification