SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME

• US 20130147540A1
• Filed: 11/30/2012
• Published: 06/13/2013
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Wu, Yifeng, Yea, Sung Hae
• Granted Patent: US 9,209,176 B2
• Time in Patent Office: Days
• US Class Current: 327/382
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48249 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0629 : in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0883 : Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03K 17/161 : in field-effect transistor switches
• CPC Class Codes: H03K 17/162 : without feedback from the output circuit to the control circuit

Abstract

Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

Claims

1. An electronic module, comprising:

a capacitor;

a first switching device comprising a first transistor, and a second switching device comprising a second transistor; and

a substrate comprising an insulating layer between a first metal layer and a second metal layer, the first metal layer including a first portion and a second portion, the second portion being electrically isolated from the first portion by a trench formed through the first metal layer between the first portion and the second portion;

wherein

the first and second switching devices are over the first metal layer; and

a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

2. The electronic module of claim 1, wherein a drain of the first transistor is electrically connected to a source of the second transistor, and the first and second transistors are both over the first portion of the first metal layer.

3. The electronic module of claim 1, wherein the first portion of the first metal layer comprises means to electrically connect the first portion of the first metal layer to a DC ground or to a first DC voltage, and the second portion of the first metal layer comprises means to electrically connect the second portion of the first metal layer to a second DC voltage.

4. The electronic module of claim 3, wherein the capacitor is configured to stabilize a voltage difference between the first and the second portions of the first metal layer.

5. The electronic module of claim 1, wherein the first or second transistor is a III-Nitride transistor.

6. The electronic component of claim 5, wherein the substrate comprises a direct bonded copper substrate.

7. The electronic module of claim 1, further comprising a second substrate comprising a second insulating layer between a third metal layer and a fourth metal layer, the second substrate being over a third portion of the first metal layer but not being over the first and second portions of the first metal layer, wherein the second substrate is between the second transistor and the first substrate, and the first transistor is over the first or second portion of the first metal layer.

8. An electronic module, comprising:

a first substrate comprising a first metal layer on a first insulating layer, the first metal layer including a first portion and a second portion;

a second substrate comprising a second insulating layer between a second metal layer and a third metal layer, the second substrate having a second surface and a third surface on an opposite side of the second substrate from the second surface, the second insulating layer having a smaller area than the first insulating layer; and

a first semiconductor device;

wherein

the second substrate is mounted over the first portion of the first metal layer without being over the second portion of the first metal layer, with the second surface of the second substrate directly contacting the first metal layer; and

the first semiconductor device is mounted on the third surface of the second substrate.

9. The electronic module of claim 8, wherein the first substrate and the second substrate comprise direct bonded copper substrates.

10. The electronic module of claim 8, further comprising a second semiconductor device mounted on the second portion of the first metal layer.

11. The electronic module of claim 10, wherein the first semiconductor device comprises a first transistor, the second semiconductor device comprises a second transistor, and a source of the first transistor and a drain of the second transistor are electrically connected to the third metal layer.

12. The electronic module of claim 11, wherein the first transistor or the second transistor is a III-Nitride transistor.

13. The electronic module of claim 11, the first metal layer further including a third portion, wherein the third portion is electrically isolated from the second portion by a trench formed through the first metal layer between the third portion and the second portion.

14. The electronic module of claim 13, further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the third portion of the first metal layer, a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, and the capacitor extends over the trench.

15. The electronic module of claim 13, wherein a drain of the first transistor is electrically connected to the third portion of the first metal layer.

16. The electronic module of claim 13, wherein the first semiconductor device further comprises a third transistor, a source of the third transistor is electrically connected to a drain of the first transistor, and a drain of the first transistor is electrically connected to the third portion of the first metal layer.

17. The electronic module of claim 10, further comprising a third substrate comprising a third insulating layer between a fourth metal layer and a fifth metal layer, the third insulating layer having a smaller area than the second insulating layer, wherein the third substrate is mounted directly over the third surface of the second substrate.

18. The electronic module of claim 17, wherein the first semiconductor device comprises a first transistor, the second semiconductor device comprises a second transistor, and a source of the first transistor and a drain of the second transistor are both electrically connected to the third metal layer.

19. The electronic module of claim 18, the first metal layer further including a third portion, wherein the third portion is electrically isolated from the second portion by a trench formed through the first metal layer between the third portion and the second portion.

20. The electronic module of claim 19, further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the third portion of the first metal layer, a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, and the capacitor extends over the trench.

21. The electronic module of claim 19, wherein a drain of the first transistor is electrically connected to the third portion of the first metal layer.

22. The electronic module of claim 19, wherein the first semiconductor device further comprises a third transistor, a source of the third transistor is electrically connected to a drain of the first transistor, and a drain of the first transistor is electrically connected to the third portion of the first metal layer.

23. The electronic module of claim 10, wherein the first and second semiconductor devices comprise transistors, the transistors being part of a half bridge.

24. A method of manufacturing an electronic module, comprising:

providing a first substrate comprising a first metal layer on a first insulating layer, the first substrate having a first surface, the first substrate including a first portion and a second portion;

providing a second substrate comprising a second insulating layer between a second metal layer and a third metal layer, the second substrate having a second surface and a third surface on an opposite side of the second substrate from the second surface;

mounting the second substrate over the first surface in the first portion of the first substrate with the second surface between the third surface and the first surface; and

mounting a first semiconductor device on the third surface of the second substrate.

25. The method of claim 24, further comprising mounting a second semiconductor device on the first surface of the first substrate in the second portion of the first substrate.

26. The method of claim 25, wherein the first semiconductor device or the second semiconductor device is a transistor.

27. The method of claim 26, wherein the transistor comprises source, gate, and drain electrodes, each of the electrodes being on a first side of the transistor.

28. The method of claim 26, wherein the transistor is a III-Nitride transistor.

29. The method of claim 25, wherein the first semiconductor device or the second semiconductor device is a switching transistor which is configured to be hard-switched.

30. The method of claim 25, wherein a switching time of the switching transistor is about 3 nanoseconds or less.

31. The method of claim 25, wherein mounting the first semiconductor device on the second substrate or mounting the second semiconductor device on the first substrate is performed prior to mounting the second substrate over the first surface in the first portion of the first substrate.

32. The method of claim 24, wherein the second surface of the second substrate is attached directly to the first surface of the first substrate in the first portion of the first substrate.

33. The method of claim 24, wherein the first surface of the first substrate comprises a surface of the first metal layer, the second surface of the second substrate comprises a surface of the second metal layer, and the third surface of the second substrate comprises a surface of the third metal layer.

34. The method of claim 24, further comprising partially removing the first metal layer.

35. The method of claim 34, wherein partially removing the first metal layer comprises forming an isolation trench through the first metal layer.

36. The method of claim 34, wherein the partially removing of the first metal layer is performed prior to mounting the second substrate over the first surface in the first portion of the first substrate.

37. The method of claim 24, wherein mounting the second substrate over the first portion of the first substrate comprises soldering the second surface of the second substrate to the first portion of the first surface of the first substrate.

38. The method of claim 24, wherein the first insulator layer or the second insulator layer comprises a ceramic material.

39. The method of claim 24, wherein one or more of the first, second, or third metal layers comprises copper.

40. The method of claim 24, wherein the first substrate or the second substrate is a direct bonded copper (DBC) substrate.

41. The method of claim 24, wherein an area of the first surface of the first substrate is larger than an area of the second surface of the second substrate.

42. The method of claim 24, wherein the electronic module comprises a half bridge.

43. The method of claim 24, wherein the electronic module comprises a power inverter or a power converter.

44. The method of claim 24, further comprising mounting a capacitor having a first terminal and a second terminal on the electronic module.

45. The method of claim 44, further comprising forming a trench through the first metal layer in the second portion of the first substrate, and wherein mounting the capacitor on the electronic module comprises connecting the first terminal to the first metal layer on a first side of the trench and connecting the second terminal to the first metal layer on a second side of the trench.

46. The method of claim 24, wherein the first substrate further comprises a fourth metal layer on an opposite side of the first insulating layer from the first metal layer.

47. An electronic module, comprising:

a first substrate comprising a first insulating layer between a first metal layer and a second metal layer;

a second substrate comprising a second insulating layer between a third metal layer and a fourth metal layer, the second substrate having a smaller area than the first substrate, the second substrate being mounted on a first portion of the first substrate with the third metal adjacent to or contacting the second metal;

a first switching device having a first gate and a first source; and

a second switching device having a second gate and a second source;

wherein

the first switching device is mounted on the second metal layer of the first substrate and the second substrate is between the second switching device and the first substrate.

48. The electronic module of claim 47, wherein the first source is electrically connected to a first source lead, the first gate is electrically connected to a first gate lead, the second source is electrically connected to a second source lead, and the second gate is electrically connected to a second gate lead.

49. The electronic module of claim 48, wherein the first source lead and first gate lead are mounted on the second metal layer of the first substrate, and the second source lead and second gate leads are mounted on the fourth metal layer of the second substrate.

50. The electronic module of claim 49, wherein the first source lead extends away from a surface of the first substrate, the second gate lead extends away from a surface of the second substrate, the first source lead includes a bend in a direction away from the second switching device, and the second gate lead includes a bend in a direction away from the first switching device.

51. An electronic device, comprising:

an enhancement-mode transistor comprising a first source electrode, a first gate electrode, a first drain electrode, and a first semiconductor layer, wherein the first source and first gate electrodes are on an opposite side of the first semiconductor layer from the first gate electrode; and

a depletion-mode transistor comprising a second source electrode and a second gate electrode, the second source electrode being over a second semiconductor layer;

wherein

the enhancement-mode transistor is mounted directly on top of or over the second source electrode, with the first drain electrode in electrical contact with the second source electrode.

52. The electronic device of claim 51, wherein the depletion-mode transistor further comprises a second drain electrode, and the second source and drain electrodes are both on a first side of the second semiconductor layer.

53. The electronic device of claim 52, wherein the depletion-mode transistor is a lateral device.

54. The electronic device of claim 53, wherein the enhancement-mode transistor is a silicon-based transistor.

55. The electronic device of claim 54, wherein the depletion-mode transistor is a III-Nitride transistor.

56. The electronic device of claim 51, wherein the first source electrode is electrically connected to the second gate electrode.

57. The electronic device of claim 51, wherein the depletion-mode transistor comprises an insulator layer on the semiconductor layer, and the second source electrode is on the insulator layer.

58. The electronic device of claim 57, the depletion-mode transistor comprising a device active area and a non-active area, wherein a device channel is in the semiconductor layer in the device active area but not in the semiconductor layer in the non-active area, and the insulator layer is over both the device active area and the non-active area.

59. The electronic device of claim 58, wherein the enhancement-mode transistor is on the insulating layer and is directly over a portion of the device active area and a portion of the non-active area.

60. The electronic device of claim 51, wherein the depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor.

61. A method of forming an electronic device, the method comprising:

providing an enhancement-mode transistor comprising a first source electrode, a first gate electrode, a first drain electrode, and a first semiconductor layer, wherein the first source and first gate electrodes are on an opposite side of the first semiconductor layer from the first gate electrode;

providing a depletion-mode transistor comprising a second source electrode and a second gate electrode, the second source electrode being over a second semiconductor layer; and

mounting the enhancement-mode transistor directly on top of or over the second source electrode, with the first drain electrode in electrical contact with the second source electrode.

62. The method of claim 61, wherein the depletion-mode transistor is a lateral device.

63. The method of claim 61, further comprising wire bonding the second gate electrode to the first source electrode.

64. A method of operating a power inverter comprising a switching device, the method comprising:

connecting the power inverter to a high voltage supply, the high voltage supply providing a voltage of at least 500V; and

switching the switching device from an off state to an on state;

wherein

in the on state the switching device conducts between 40 and 50 Amps;

in the off state the switching device blocks the voltage provided by high voltage supply;

a switching time of the switching is less than 10 nanoseconds; and

the voltage across the switching device never exceeds 1.35 times the voltage provided by the high voltage supply.

65. The method of claim 64, wherein the switching time is less than 5 nanoseconds.

66. The method of claim 64, wherein the voltage across the switching device never exceeds 700V.