Analogue to Digital Converter, An Integrated Circuit and Medical Device

• US 20130147649A1
• Filed: 05/25/2011
• Published: 06/13/2013
• Est. Priority Date: 05/26/2010
• Status: Active Grant

• Current Assignee: Agency For Science Technology and Research
• Original Assignee: Agency For Science Technology and Research
• Inventors: Khannur, Pradeep Basappa, Chan, Kok Lim, Je, Minkyu, Cheong, Jiahao
• Granted Patent: US 8,786,484 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: H03M 1/0682 using a differential network structure, i.e. symmetrical with respect to ground
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/466 using switched capacitors

Abstract

An analogue to digital converter comprises a first input connection to receive a first part of the analogue input signal; a second input connection to receive a second part of the analogue input signal; a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors; wherein, during a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors, the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors, and a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal.

Claims

1. An analogue-to-digital converter for converting an analogue input signal into a digital output signal, the analogue-to-digital converter comprising:

a first input connection configured to receive a first part of the analog input signal;

a second input connection configured to receive a second part of the analogue input signal;

a first plurality of capacitors and a second plurality of capacitors, each capacitor of the first and second plurality of capacitors having a first contact and a second contact, each capacitor of the first plurality of capacitors having a corresponding capacitor in the second plurality of capacitors to form a plurality of capacitor pairs;

a switching array coupled to the second contact of each capacitor in the first and second plurality of capacitors; and

,

switching logic for controlling the switching array;

wherein, during a sampling period of the analogue-to-digital converter, the first input connection is configured to couple the first part of the analogue input signal to the first contact of each capacitor of the first plurality of capacitors, the second input connection is configured to couple the second part of the analogue input signal to the first contact of each capacitor of the second plurality of capacitors, and the switching logic is configured to cause the switching array to couple the second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal.

2. The analogue-to-digital converter of claim 1, wherein, during a conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of at least one capacitor pair to a different one of a first and a second reference voltage, and to couple the other capacitors in capacitor pairs via their second contacts to determine subsequent bits of the digital output signal.

3. The analogue-to-digital converter of claim 2, wherein, during the conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of a first capacitor pair to a different one of the first and the second reference voltage depending on the determination of the first bit of the digital output signal, and to couple in pairs any succeeding capacitor pairs to determine a second bit of the digital output signal.

4. The analogue-to-digital converter of claim 3, wherein, during the conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of an ith capacitor pair to a different one of the first and the second reference voltage depending on a determination of an ith bit of the digital output signal, and to couple in pairs any succeeding capacitor pairs to determine an (i+1)th bit of the digital output signal.

5. The analogue-to-digital converter of claim 2, wherein, during the conversion period of the analogue-to-digital converter, the first input connection is configured to decouple the first part of the analogue input signal from the first contact of each capacitor of the first plurality of capacitors, the second input connection is configured to decouple the second part of the analogue input signal from the first contact of each capacitor of the second plurality of capacitors.

6. The analogue-to-digital converter of claim 1, wherein the switching array is configured to selectively couple the second contact of each capacitor in the first plurality of capacitors to one of the first reference voltage, the second reference voltage, the common mode voltage and its corresponding capacitor in the second plurality of capacitors, and to selectively couple the second contact of each capacitor in the second plurality of capacitors to one of the first reference voltage, the second reference voltage, the common mode voltage, and its corresponding capacitor in the first plurality of capacitors.

7. The analogue-to-digital converter of claim 1, further comprising a comparator having a first input terminal coupled to the first contact of each capacitor of the first plurality of capacitors, and a second input terminal coupled to the first contact of each capacitor of the second plurality of capacitors.

8. The analogue-to-digital converter of claim 7, wherein the comparator further comprises an output, wherein the switching logic is configured to control the switching array in dependence on the comparator output.

9. The analogue-to-digital converter of claim 8, wherein the analogue-to-digital converter is configured to determine bits of the digital output signal in dependence on the comparator output.

10. The analogue-to-digital converter of claim 7, wherein the comparator is a time-domain comparator comprising voltage controlled delay circuitry configured to convert a voltage level of the time-domain comparator to a delay of a clock signal, and phase detection circuitry configured to determine which of the signals input on the first input terminal and the second input terminal changes earlier.

11. The analogue-to-digital converter of claim 1, wherein the first plurality of capacitors comprises capacitance values in a non-binary weighted relationship.

12. The analogue-to-digital converter of claim 1, wherein the second plurality of capacitors comprises capacitance values in a non-binary weighted relationship.

13. The analogue-to-digital converter of claim 1, wherein both capacitors of a capacitor pair have the same capacitance.

14. The analogue-to-digital converter of claim 2, wherein the digital output signal comprises N bits and each of the first plurality of capacitors and the second plurality of capacitors comprise more than N+1 capacitors to provide redundancy.

15. The analogue-to-digital converter of claim 1, wherein the second reference voltage is ground.

16. The analogue-to-digital converter of claim 1, further comprising a reset switch, wherein the switching logic is configured to cause the reset switch to regulate the common mode voltage.

17. The analogue-to-digital converter of claim 1, wherein the first bit is a most significant bit of the digital output signal.

18. The analogue-to-digital converter of claim 1, wherein the first part of the analogue input signal and the second part of the analogue input signal comprise the analogue input signal in differential form.

19. The analogue-to-digital converter of claim 18, wherein the first reference voltage is selected to be equal to a common mode voltage of the analogue input signal in differential form, such that capacitors that are coupled in pairs have a value of half of the first reference voltage at their second contact during the conversion period

21. An integrated circuit comprising the analogue-to-digital converter of claim 1.

20. (canceled)

22. (canceled)