Z-Direction Decoding for Three Dimensional Memory Array

• US 20130148427A1
• Filed: 12/13/2011
• Published: 06/13/2013
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lee, Guanru
• Granted Patent: US 8,570,806 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular level of a three dimensional memory array are selected. The NAND strings on other levels are deselected.

Claims

1. An integrated circuit comprising:

a three dimensional memory array including a plurality of levels, levels in the plurality of levels including respective two dimensional arrays of NAND strings, the NAND strings including memory cells and switch transistors, the switch transistors having combinations of threshold voltage levels that vary across the plurality of levels;

a plurality of select lines electrically coupled to the switch transistors; and

control circuitry applying a bias arrangement to the plurality of select lines such that the NAND strings on a particular level of the plurality of levels are selected by the switch transistors, and the NAND strings on other levels of the plurality of levels are deselected by the switch transistors.

2. The integrated circuit of claim 1, wherein threshold voltages of the switch transistors controlled by one of the plurality of select lines are from a quantity of switch threshold voltage levels, and the quantity of threshold voltage levels is equal to a number of levels in the plurality of levels of the three dimensional array.

3. The integrated circuit of claim 1, wherein the plurality of select lines includes two select lines, and the switch transistors electrically coupled to the two select lines distinguish the NAND strings on the particular level from the NAND strings on the other levels of the plurality of levels.

4. The integrated circuit of claim 1, wherein threshold voltages of the switch transistors controlled by one of the plurality of select lines are from a quantity of switch threshold voltage levels, and the quantity of threshold voltage levels is equal to a square root of a number of levels in the plurality of levels of the three dimensional array.

5. The integrated circuit of claim 1, wherein the plurality of select lines includes four select lines, and the switch transistors electrically coupled to the four select lines distinguish NAND strings on the particular level from the NAND strings on the other levels of the plurality of levels.

6. The integrated circuit of claim 1, wherein threshold voltages of the switch transistors coupled to different select lines of the plurality of select lines are from corresponding sets of switch threshold voltage levels.

7. The integrated circuit of claim 1, wherein the plurality of select lines includes a first select line and a second select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, and a second set of switch transistors electrically coupled to the second select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, and a second switch transistor from the second set of switch transistors,

threshold voltages of the first set of switch transistors are from a first set of switch threshold voltage levels having a quantity of switch threshold voltage levels,

threshold voltages of the second set of switch transistors are from a second set of switch threshold voltage levels having the quantity of switch threshold voltage levels, and

a number of levels in the plurality of levels of the three dimensional array is equal to the quantity of switch threshold voltage levels.

8. The integrated circuit of claim 1, wherein the plurality of select lines includes a first select line, a second select line, a third select line, and a fourth select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, a second set of switch transistors electrically coupled to the second select line, a third set of switch transistors electrically coupled to the third select line, and a fourth set of switch transistors electrically coupled to the fourth select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, a second switch transistor from the second set of switch transistors, a third switch transistor from the third set of switch transistors, and a fourth switch transistor from the fourth set of switch transistors,

threshold voltages of the first set of switch transistors are from a first set of switch threshold voltage levels having a first quantity of switch threshold voltage levels,

threshold voltages of the second set of switch transistors are from a second set of switch threshold voltage levels having the first quantity of switch threshold voltage levels,

threshold voltages of the third set of switch transistors are from a third set of switch threshold voltage levels having a second quantity of switch threshold voltage levels,

threshold voltages of the fourth set of switch transistors are from a fourth set of switch threshold voltage levels having the second quantity of switch threshold voltage levels and

a number of levels in the plurality of levels of the three dimensional array is equal to a product of the first quantity of switch threshold voltage levels and the second quantity of threshold voltage levels.

9. The integrated circuit of claim 1, wherein the plurality of select lines includes a first select line and a second select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, and a second set of switch transistors electrically coupled to the second select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors and a second switch transistor from the second set of switch transistors,

threshold voltages of the first set of switch transistors are paired with threshold voltages of the second set of switch transistors, a first threshold voltage of the first switch transistors on the particular level at an i-th threshold voltage level in a first set of N increasingly ordered threshold voltage levels, is paired with a second threshold voltage of the second switch transistors on the particular level at an i-th threshold voltage level in a second set of N decreasingly ordered threshold voltage levels.

10. The integrated circuit of claim 1, wherein the plurality of select lines includes a first select line, a second select line, a third select line, and a fourth select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, a second set of switch transistors electrically coupled to the second select line, a third set of switch transistors electrically coupled to the third select line, and a fourth set of switch transistors electrically coupled to the fourth select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, a second switch transistor from the second set of switch transistors, a third switch transistor from the third set of switch transistors, and a fourth switch transistor from the fourth set of switch transistors,

threshold voltages of the first set of switch transistors, the second set of switch transistors, the third set of switch transistors, and the fourth set of switch transistors are from corresponding sets of switch threshold voltage levels having N switch threshold voltage levels, and

threshold voltages of the first set of switch transistors are paired with threshold voltages of the second set of switch transistors, such that the bias arrangement applied to the first select line and the second select line selects the NAND strings on a fraction (1/N) of the plurality of levels,

threshold voltages of the third set of switch transistors are paired with threshold voltages of the fourth set of switch transistors, such that the bias arrangement applied to the third select line and the fourth select line selects the NAND strings on the fraction (1/N) of the plurality of levels, and

an intersection of the NAND strings selected by the first select line and the second select line, and the NAND strings selected by the third select line and the fourth select line, selects the NAND strings on the particular level of the plurality of levels.

11. A method comprising:

selecting NAND strings including memory cells and switch transistors on a particular level of a plurality of levels of a three dimensional memory array, and deselecting NAND strings on other levels of the plurality of levels, by applying a bias arrangement to a plurality of select lines electrically coupled to the switch transistors having combinations of threshold voltage levels that vary across the plurality of levels.

12. The method of claim 11, wherein threshold voltages of the switch transistors controlled by one of the plurality of select lines are from a quantity of switch threshold voltage levels, and the quantity of threshold voltage levels is equal to a number of levels in the plurality of levels of the three dimensional array.

13. The method of claim 11, wherein the plurality of select lines includes two select lines, and the switch transistors electrically coupled to the two select lines distinguish the NAND strings on the particular level from the NAND strings on the other levels of the plurality of levels.

14. The method of claim 11, wherein threshold voltages of the switch transistors controlled by one of the plurality of select lines are from a quantity of switch threshold voltage levels, and the quantity of threshold voltage levels is equal to a square root of a number of levels in the plurality of levels of the three dimensional array.

15. The method of claim 11, wherein the plurality of select lines includes four select lines, and the switch transistors electrically coupled to the four select lines distinguish NAND strings on the particular level from the NAND strings on the other levels of the plurality of levels.

16. The method of claim 11, wherein threshold voltages of the switch transistors coupled to different select lines of the plurality of select lines are from corresponding sets of switch threshold voltage levels.

17. The method of claim 11, wherein the plurality of select lines includes a first select line and a second select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, and a second set of switch transistors electrically coupled to the second select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, and a second switch transistor from the second set of switch transistors,

threshold voltages of the first set of switch transistors are from a first set of switch threshold voltage levels having a quantity of switch threshold voltage levels,

threshold voltages of the second set of switch transistors are from a second set of switch threshold voltage levels having the quantity of switch threshold voltage levels, and

a number of levels in the plurality of levels of the three dimensional array is equal to the quantity of switch threshold voltage levels.

18. The method of claim 11, wherein the plurality of select lines includes a first select line, a second select line, a third select line, and a fourth select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, a second set of switch transistors electrically coupled to the second select line, a third set of switch transistors electrically coupled to the third select line, and a fourth set of switch transistors electrically coupled to the fourth select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, a second switch transistor from the second set of switch transistors, a third switch transistor from the third set of switch transistors, and a fourth switch transistor from the fourth set of switch transistors,

threshold voltages of the first set of switch transistors are from a first set of switch threshold voltage levels having a first quantity of switch threshold voltage levels,

threshold voltages of the second set of switch transistors are from a second set of switch threshold voltage levels having the first quantity of switch threshold voltage levels,

threshold voltages of the third set of switch transistors are from a third set of switch threshold voltage levels having a second quantity of switch threshold voltage levels,

threshold voltages of the fourth set of switch transistors are from a fourth set of switch threshold voltage levels having the second quantity of switch threshold voltage levels and

a number of levels in the plurality of levels of the three dimensional array is equal to a product of the first quantity of switch threshold voltage levels and the second quantity of threshold voltage levels.

19. The method of claim 11, wherein the plurality of select lines includes a first select line and a second select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, and a second set of switch transistors electrically coupled to the second select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors and a second switch transistor from the second set of switch transistors,

threshold voltages of the first set of switch transistors are paired with threshold voltages of the second set of switch transistors, a first threshold voltage of the first switch transistors on the particular level at an i-th threshold voltage level in a first set of N increasingly ordered threshold voltages, is paired with a second threshold voltage of the second switch transistors on the particular level at an i-th threshold voltage level in a second set of N decreasingly ordered threshold voltage levels.

20. The method of claim 11, wherein the plurality of select lines includes a first select line, a second select line, a third select line, and a fourth select line,

the switch transistors include a first set of switch transistors electrically coupled to the first select line, a second set of switch transistors electrically coupled to the second select line, a third set of switch transistors electrically coupled to the third select line, and a fourth set of switch transistors electrically coupled to the fourth select line,

the NAND strings include memory cells in series with a first switch transistor from the first set of switch transistors, a second switch transistor from the second set of switch transistors, a third switch transistor from the third set of switch transistors, and a fourth switch transistor from the fourth set of switch transistors,

threshold voltages of the first set of switch transistors, the second set of switch transistors, the third set of switch transistors, and the fourth set of switch transistors are from corresponding sets of switch threshold voltage levels having N switch threshold voltage levels, and

threshold voltages of the first set of switch transistors are paired with threshold voltages of the second set of switch transistors, such that the bias arrangement applied to the first select line and the second select line selects the NAND strings on a fraction (1/N) of the plurality of levels,

threshold voltages of the third set of switch transistors are paired with threshold voltages of the fourth set of switch transistors, such that the bias arrangement applied to the third select line and the fourth select line selects the NAND strings on the fraction (1/N) of the plurality of levels, and

an intersection of the NAND strings selected by the first select line and the second select line, and the NAND strings selected by the third select line and the fourth select line, selects the NAND strings on the particular level of the plurality of levels.