SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUED DATA

• US 20130148436A1
• Filed: 07/09/2012
• Published: 06/13/2013
• Est. Priority Date: 12/12/2011
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Yasuhiko Kurosawa
• Inventors: KUROSAWA, Yasuhiko
• Application Number:
  US13/544,147
• Publication Number:
  US 20130148436A1
• Time in Patent Office: Days
• US Class Current: 365/185.24
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set. The controller reads data from the memory. The controller reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells, calculates difference data on data read at each of the threshold voltages, calculates a minimum value of the distribution of the threshold voltages from the difference data, calculates a range of threshold voltages lower than the minimum value based on the minimum value, and sets a central voltage in the calculated range of threshold voltages as a read voltage.

Claims

1. A semiconductor memory device comprising:

a memory which includes a plurality of memory cells, each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set; and

a controller which reads data from the memory and which

reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells,

calculates difference data on data read at each of the threshold voltages,

calculates a minimum value of the distribution of the threshold voltages from the difference data,

calculates a range of threshold voltages lower than the minimum value based on the minimum value, and

sets a central voltage in the calculated range of threshold voltages as a read voltage.

2. The semiconductor memory device of claim 1, wherein the controller calculates a weighted average of the difference data and calculates a minimum value of a distribution of the threshold voltages from the weighted average data.

3. The semiconductor memory device of claim 2, wherein the controller adds a margin to the minimum value to set a threshold value when calculating a range of threshold voltages lower than the minimum value based on the minimum value and calculates a range of threshold voltages lower than the threshold value.

4. The semiconductor memory device of claim 1, wherein the controller reads data “

1”

from the memory cells at each of the threshold voltages in the read operation and counts the number of the data “

1”

s at each of the threshold voltages.

5. The semiconductor memory device of claim 4, wherein the controller calculates difference data on the number of the data “

1”

s counted at each of the threshold voltages.

6. A semiconductor memory device comprising:

a memory which includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set; and

a controller which reads data from the memory and which

reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells,

calculates difference data on data read at each of the threshold voltages,

calculates a maximum value of the distribution of the threshold voltages from the difference data,

calculates a range of threshold voltages higher than the maximum value based on the minimum value, and

sets a central voltage in the calculated range of threshold voltages as a read voltage.

7. The semiconductor memory device of claim 6, wherein the controller calculates a weighted average of the difference data and calculates a maximum value of a distribution of the threshold voltages from the weighted average data.

8. The semiconductor memory device of claim 6, wherein the controller reads data “

1”

from the memory cells at each of the threshold voltages in the read operation and counts the number of the data “

1”

s at each of the threshold voltages.

9. The semiconductor memory device of claim 8, wherein the controller calculates difference data on the number of the data “

1”

s counted at each of the threshold voltages.

10. A semiconductor memory device comprising:

a memory which includes a plurality of memory cells each of which stores data when one of an n number of threshold voltages (n being a natural number not less than two) is set; and

a controller which reads data from the memory and which

reads data from the memory cells at each of the threshold voltages in a read operation that checks a distribution of threshold voltages of the memory cells,

calculates difference data on data read at each of the threshold voltages,

performs a first search operation of detecting a threshold voltage corresponding to a maximum value higher than a first threshold value based on the difference data and further detecting threshold voltages which are lower than a second threshold value and correspond to a first and a second minimum value lying on both sides of the maximum value,

sets a first and a second bottom region including the first and second minimum values based on the threshold values corresponding to the first and second minimum values detected in the first search operation and performing a second search operation, and

detects threshold voltages corresponding to minimum values of a first and a second threshold voltage from the central positions of the first and second bottom regions.

11. The semiconductor memory device of claim 10, wherein the first and second bottom regions are set in such a manner that a margin is added to the first and second minimum values, respectively.

12. The semiconductor memory device of claim 11, wherein the threshold voltage corresponding to the first minimum value is obtained by subtracting the difference between a threshold voltage corresponding to the top and a threshold voltage of a top adjacent to a position with a lower threshold voltage than that of the top from the threshold voltage corresponding to the top, and

the threshold voltage corresponding to the second minimum value is obtained by adding the difference between the threshold voltage corresponding to the top and a threshold voltage of a top adjacent to a position with a higher threshold voltage than that of the top to the threshold voltage corresponding to the top.

13. The semiconductor memory device of claim 10, wherein the controller, when searching for a threshold voltage of a bottom of a distribution, draws two straight lines from both ends of difference data in a search range toward a point where difference data becomes “

0”

so that the lines may cross each other and estimates the intersection of the two straight lines to be a bottom of the distribution.

14. The semiconductor memory device of claim 10, wherein the first and second bottom regions are set in such a manner that a margin is added to the first and second minimum values obtained in the first search operation, respectively.

15. The semiconductor memory device of claim 10, further comprising a first table in which threshold values are set so as to correspond to values of the top of the distribution.

16. The semiconductor memory device of claim 15, wherein the controller selects threshold values in the first table based on a maximum value obtained in the first search operation and sets the first and second bottom regions.

17. The semiconductor memory device of claim 10, further comprising a second table in which correction values of the position of the bottom are set so as to correspond to the position of the top.

18. The semiconductor memory device of claim 17, wherein the controller selects a correction value of the position of the bottom in the second table based on the position of the top and estimates the position of the bottom.

19. The semiconductor memory device of claim 10, wherein the controller reads data “

1”

from the memory cells at each of the threshold voltages in the read operation and counts the number of the data “

1”

s at each of the threshold voltages.

20. The semiconductor memory device of claim 19, wherein the controller calculates difference data on the number of the data “

1”

s counted at each of the threshold voltages.