THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT

• US 20130148437A1
• Filed: 12/22/2012
• Published: 06/13/2013
• Est. Priority Date: 11/29/2006
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Haukness, Brent S., Horowitz, Mark A., Kellam, Mark D., Bronner, Gary B., Assaderaghi, Fariborz
• Application Number:
  US13/726,042
• Publication Number:
  US 20130148437A1
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence

Abstract

In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.

Claims

1. A method of operation within an integrated-circuit memory device having charge-storing memory cells, the method comprising:

detecting an event during operation of the integrated-circuit memory device; and

in response to detecting the event, enabling electric current to flow through a word line coupled to the charge-storing memory cells for a limited interval to heat the charge-storing memory cells to an annealing temperature range above 250°

C., the limited interval ranging from an interval shorter than required to erase contents of the charge-storing memory cells to an interval not substantially longer than required to erase contents of the charge-storing memory cells.

2. The method of claim 1 wherein detecting an event comprises receiving an erase command instructing the integrated-circuit memory device to erase the contents of the charge-storing memory cells.

3. The method of claim 2 further comprising erasing the contents of the charge-storing memory cells in response to receiving the erase command, and wherein enabling the electric current to flow through the word line coupled to the charge-storing memory cells for the limited interval comprises enabling the electric current to flow the word line concurrently with erasing the contents of the charge-storage memory cells.

4. The method of claim 2 further comprising, in response to the erase command, performing an erase operation during a first time period with respect to the charge-storing memory cells, and wherein enabling the electric current to flow through the word line coupled to the charge-storing memory cells for the limited interval comprises enabling the electric current to flow through the word line at a predetermined time with respect to the first time period.

5. The method of claim 2 further comprising:

receiving additional erase commands, each of the additional erase commands instructing the integrated-circuit memory device to erase the charge-storing memory cells; and

in response to each of the additional erase commands;

erasing the charge-storing memory cells, and

enabling electric current to flow through the word line coupled to the charge-storing cells to heat the charge-storing cells to the annealing temperature range.

6. The method of claim 1 wherein the interval not substantially longer than required to erase contents of the charge-storing memory cells is less than one second.

7. The method of claim 1 further comprising raising the voltage of a substrate of the integrated circuit device to a potential that enables stored charge to be discharged from the charge-storage cells concurrently with enabling the electric current to flow through the word line coupled to the charge-storing memory cells.

8. The method of claim 1 further comprising asserting a signal on the word line to enable a data read operation with respect to one or more of the charge-storing memory cells.

9. The method of claim 1 wherein the charge-storing memory cells comprise silicon-oxide-nitride-oxide-silicon (SONOS) memory cells.

10. The method of claim 1 wherein the charge-storing memory cells comprise floating-gate memory cells.

11. The method of claim 1 wherein detecting the event comprises receiving an address value that corresponds to the word line.

12. A method of operation within an integrated-circuit memory device, the method comprising:

receiving a sequence of erase commands, each erase command instructing an erase operation with respect to charge-storing memory cells within the integrated-circuit memory device; and

in response to each of the erase commands;

performing an erase operation with respect to the charge-storing memory cells, and performing a thermal anneal operation with respect to the charge-storing memory cells.

13. The method of claim 12 wherein performing a thermal anneal operation with respect to the charge-storing memory cells comprises enabling electric current to flow through a word line coupled to the charge-storing memory cells to heat the charge-storing memory cells to an annealing temperature range.

14. The method of claim 13 wherein enabling electric current to flow through the word line coupled to the charge-storing memory cells to heat the charge-storing memory cells to the annealing temperature range comprises enabling the electric current to flow for a time ranging from an interval shorter than required to erase contents of the charge-storing memory cells to an interval not substantially longer than required to erase contents of the charge-storing memory cells, and wherein the annealing temperature range comprises a temperature range above 250°

C.

15. An integrated-circuit memory device comprising:

charge-storing memory cells;

a word line coupled to the charge-storing memory cells;

control circuitry to output one or more control signals in response to detecting an event during operation of the integrated-circuit memory device; and

annealing circuitry to enable electric current to flow through the word line for a limited interval to heat the charge-storing memory cells to an annealing temperature range above 250°

C., the limited interval ranging from an interval shorter than required to erase contents of the charge-storing memory cells to an interval not substantially longer than required to erase contents of the charge-storing memory cells.

16. The integrated-circuit memory device of claim 15 further comprising circuitry to assert a select signal on the word line to enable data to be read out of one or more of the charge-storing memory cells.

17. The integrated-circuit memory device of claim 15 wherein the control circuitry to output one or more control signals in response to detecting an event comprises control circuitry to output one or more control signals in response to receiving an erase command, the erase command instructing the integrated-circuit memory device to erase the contents of the charge-storing memory cells.

18. An integrated-circuit memory device comprising:

charge-storing memory cells;

control circuitry to receive a sequence of erase commands, each erase command instructing an erase operation with respect to the charge-storing memory cells; and

circuitry to perform, in response to each of the erase commands, an erase operation with respect to the charge-storing memory cells and a thermal anneal operation with respect to the charge-storing memory cells.

19. The integrated-circuit memory device of claim 18 further comprising a word line coupled to the charge-storing memory cells, and wherein the circuitry to perform the thermal anneal operation with respect to the charge-storing memory cells comprises circuitry to enable electric current to flow through the word line to heat the charge-storing memory cells to an annealing temperature range.

20. The integrated-circuit memory device of claim 19 wherein the circuitry to enable the electric current to flow through the word line coupled to the charge-storing memory cells to heat the charge-storing memory cells to the annealing temperature range comprises circuitry to enable the electric current to flow for a time ranging from an interval shorter than required to erase contents of the charge-storing memory cells to an interval not substantially longer than required to erase contents of the charge-storing memory cells, and wherein the annealing temperature range comprises a temperature range above 250°

C.