PREDICTABLE CODING DELAY OVER COMMUNICATIONS NETWORKS

• US 20130148768A1
• Filed: 12/07/2011
• Published: 06/13/2013
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: GatesAir Incorporated (Groupe Sipromad SA)
• Original Assignee: Junius Adonis Kim
• Inventors: KIM, JUNIUS ADONIS
• Granted Patent: US 8,971,471 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04H 20/67 Common-wave systems, i.e. using separate transmitters operating on substantially the same frequency
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer

Abstract

A decoder includes a buffer configured to incrementally transport a synchronous data stream through a path of the decoder. A control circuit is configured to control a depth parameter associated with the buffer and to provide a substantially predictable delay of the synchronous data stream through the path of the decoder.

Claims

1. A decoder, comprising:

a buffer configured to incrementally transport a synchronous data stream through a path of the decoder; and

a control circuit configured to control a depth parameter associated with the buffer and to provide a substantially predictable delay of the synchronous data stream through the path of the decoder.

2. The decoder of claim 1, wherein the buffer is a first-in first-out (FIFO) circuit configured to clock the synchronous data stream through the path of the buffer.

3. The decoder of claim 1, wherein the depth parameter is maintained such that a fill rate and a depletion rate of the buffer are at about equal rates.

4. The decoder of claim 3, wherein the depth parameter is a fill level indicating a number of storage locations in the buffer that have received at least a portion of the synchronous data stream.

5. The decoder of claim 4, wherein the fill level is assigned a threshold value that includes at least one of an underrun limit, a minimum fill level, a maximum fill level, or an overrun limit.

6. The decoder of claim 1, wherein the predictable delay is increased by moving data into the buffer or decreased by removing data from the buffer in an asynchronous manner to buffer clock operations.

7. The decoder of claim 1, wherein the predictable delay is increased or decreased by adjusting clock frequencies to the buffer.

8. The decoder of claim 1, further comprising an average depth measurement component that provides the control circuit an average depth measurement of storage locations in the buffer, the control circuit adjusts clock frequencies to the buffer to control the predictable delay based on the average depth measurement.

9. The decoder of claim 8,

wherein the control circuit determines a target delay for the buffer and determines a delay error that is a difference between a measured delay for the buffer and the target delay,

wherein the control circuit mitigates the delay error by adjusting the clock frequencies to the buffer based on the average depth measurement.

10. The decoder of claim 9, further comprising a programmable divider that is controlled by the control circuit to adjust the clock frequencies to the buffer.

11. The decoder of claim 10, further comprising a frequency locked loop that receives network timing recovered from an input data stream of a single frequency network, the frequency locked loop being configured to generate input timing for the programmable divider.

12. The decoder of claim 11, further comprising an oscillator configured to generate the input timing for the programmable divider based on a control signal from the frequency locked loop.

13. The decoder of claim 1, wherein the decoder is configured as part of a system, wherein the system further comprises an encoder that employs an encoder buffer to provide a substantially predictable delay for data packets that are transmitted to the decoder over a single frequency network (SFN).

14. The system of claim 13, the encoder further comprising a frequency locked loop and a phased locked loop to generate timing for the encoder buffer and provide the substantially predictable delay for the data packets.

15. The decoder of claim 1, wherein the control circuit derives synchronous network timing by monitoring the depth parameter according to an average fill level of the buffer over time.

16. A device, comprising:

a decoder configured to decode synchronous data packets from a single frequency network (SFN);

a first-in first-out (FIFO) circuit configured to introduce a substantially predictable delay for the synchronous data packets received from the decoder; and

a control circuit configured to adjust a depth parameter that is proportional to the predictable delay, wherein the depth parameter is based on an average depth measurement of storage locations in the FIFO circuit that currently store the synchronous data packets.

17. The device of claim 16, further comprising a frequency locked loop to provide timing for the synchronous data packets that pass through the FIFO circuit.

18. The device of claim 16, wherein the control circuit adjusts the depth parameter such that a fill rate and a depletion rate for the FIFO circuit are maintained about equal as averaged over time.

19. A method, comprising:

storing a synchronous data stream from a single frequency network into a buffer of a decoder;

measuring an average depth measurement corresponding to storage locations that are filled in the buffer by the synchronous data stream, the average depth measurement being proportional to a delay in a path through the decoder;

determining an error parameter that is a difference between the average depth measurement and a target parameter representing a desired delay; and

reducing the error parameter in order to control the delay predictably.

20. The method of claim 19, further comprising emptying an encoder first-in first-out (FIFO) circuit in a periodic manner resulting in a corresponding delay characteristic of an encode process that is predictable and known a priori.