Interrupt Moderation

• US 20130151744A1
• Filed: 02/07/2013
• Published: 06/13/2013
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Gupta, Somesh, Nagapudi, Venkatesh
• Granted Patent: US 8,677,042 B2
• Time in Patent Office: Days
• US Class Current: 710/263
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day

Abstract

A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Claims

1. An interrupt handler, comprising:

a plurality of interrupt blocks, each comprising a first timer; and

interrupt coalescing logic, comprising;

first timer initialization logic, configured to initialize the first timer to a first predetermined value;

interrupt condition logic;

first timer expiration logic, configured to trigger an interrupt upon expiration of the first timer if the interrupt condition logic indicates an interrupt condition exists; and

first timer reset logic, configured to cause the first timer initialization logic to initialize the first timer upon expiration of the first timer if the interrupt condition logic indicates no interrupt condition exists.

2. The interrupt handler of claim 1, further comprising:

interrupt acknowledgment logic, adapted to cause the first timer initialization logic to initialize the first timer responsive to receiving an interrupt acknowledgment.

3. The interrupt handler of claim 1, wherein the first timer expiration logic is further configured to keep the first timer in an expired state after triggering an interrupt until receipt of an interrupt acknowledgement.

4. The interrupt handler of claim 1, wherein the first timer initialization logic starts the first timer independent of the existence of an interrupt condition.

5. The interrupt handler of claim 1, further comprising:

a plurality of queues; and

an index table, configured for storing information for servicing interrupts responsive to events corresponding to the plurality of queues,

wherein each of the plurality of interrupt blocks is associated with one or more of the plurality of queues and updated responsive to events corresponding to the one or more associated queues.

6. The interrupt handler of claim 5,

wherein each of the plurality of interrupt blocks further comprises:

a second timer; and

a first counter, updated responsive to events corresponding to the one or more associated queues,

wherein the interrupt condition logic indicates an interrupt condition upon expiration of the second timer, and

wherein the interrupt condition logic indicates an interrupt condition upon the first counter reaching a predetermined counter value.

7. The interrupt handler of claim 5,

wherein each of the plurality of interrupt blocks further comprises:

a first counter, updated responsive to events corresponding to the one or more associated queues,

wherein the interrupt handler further comprises;

a data transfer logic, configured to transfer information from the index table upon either the first counter reaching a predetermined counter value or the triggering of an interrupt by the first timer expiration logic.

8. The interrupt handler of claim 5, wherein the plurality of queues comprises:

a plurality of receive queues;

a plurality of transmit queues; and

a plurality of completion queues, each associated with at least one of the plurality of receive queues,

wherein each of the plurality of transmit queues is associated with an interrupt block of the plurality of interrupt blocks, and

wherein each of the plurality of completion queues is associated with an interrupt block of the plurality of interrupt blocks.

9. A peripheral device, comprising:

a queue manager, comprising;

a plurality of interrupt blocks, each comprising;

a first timer;

an index table, configured for storing information for servicing interrupts responsive to events; and

interrupt coalescing logic, comprising;

first timer initialization logic, configured to initialize the first timer of an interrupt block of the plurality of interrupt blocks to a first predetermined value associated with the interrupt block;

interrupt condition logic;

first timer expiration logic, configured to trigger an interrupt upon expiration of the first timer if the interrupt condition logic indicates an interrupt condition exists; and

first timer reset logic, configured to cause the first timer initialization logic to initialize the first timer upon expiration of the first timer if the interrupt condition logic indicates no interrupt condition exists.

10. The peripheral device of claim 9, wherein the interrupt coalescing logic further comprises:

interrupt acknowledgment logic, adapted to cause the first timer initialization logic to initialize the first timer responsive to receiving an interrupt acknowledgment.

11. The peripheral device of claim 9, wherein the first timer expiration logic is further configured to keep the first timer in an expired state after triggering an interrupt until receipt of an interrupt acknowledgement.

12. The peripheral device of claim 9, wherein the first timer initialization logic is configured to start the first timer independent of the existence of an interrupt condition.

13. The peripheral device of claim 9, further comprising:

receive agent logic, coupled to the queue manager; and

transmit agent logic, coupled to the queue manager,

wherein the queue manager further comprises;

a plurality of queues each configurably associated with the receive agent logic or the transmit agent logic, and

wherein each of the plurality of interrupt blocks is associated with one or more of the plurality of queues and updated responsive to events corresponding to the one or more associated queues.

14. The peripheral device of claim 13,

wherein each of the plurality of interrupt blocks further comprises:

a second timer; and

a first counter, updated responsive to events corresponding to the one or more associated queues,

wherein the interrupt condition logic indicates an interrupt condition upon expiration of the second timer, and

wherein the interrupt condition logic indicates an interrupt condition upon the first counter reaching a predetermined counter value.

15. The peripheral device of claim 13,

wherein each of the plurality of interrupt blocks further comprises:

a first counter, updated responsive to events corresponding to the one or more associated queues,

wherein the queue manager further comprises;

a data transfer logic, configured to transfer information from the index table upon either the first counter reaching the first predetermined counter value or the triggering of an interrupt by the first timer expiration logic.

16. The peripheral device of claim 13, wherein the plurality of queues comprises:

a plurality of receive queues, associated with the receive agent logic;

a plurality of transmit queues, associated with the transmit agent logic; and

a plurality of completion queues, each associated with at least one of the plurality of receive queues,

wherein each of the plurality of transmit queues is associated with an interrupt block of the plurality of interrupt blocks, and

wherein each of the plurality of completion queues is associated with an interrupt block of the plurality of interrupt blocks.

17. The peripheral device of claim 13, further comprising:

configuration logic, adapted to associate one or more of the plurality of queues with an interrupt block of the plurality of interrupt blocks.

18. The peripheral device of claim 9, further comprising:

configuration logic, adapted to associate a message-signaled interrupt vector with an interrupt block of the plurality of interrupt blocks.

19. The peripheral device of claim 9, wherein the first predetermined value for each of the plurality of interrupt blocks is independently configurable.

20. The peripheral device of claim 9, wherein the interrupt condition logic comprises:

configuration logic to configure interrupt conditions independently for each of the plurality of interrupt blocks.